The ATLAS SCT: Commissioning experience and SLHC upgrade

The ATLAS Semiconductor Tracker (SCT) has been installed, and fully connected to electrical, optical and cooling services. Commissioning has been performed both with calibration data and cosmic ray events. The cosmics were used to align the detector, measure the hit efficiency and set the timing. The SCT is now ready to take data when the LHC turns on this autumn. At the same time, it is clear that the present ATLAS tracker will need to be renewed for projected luminosity upgrade of the LHC, the SLHC. This is mainly driven by occupancy and radiation hardness issues. The new tracker will likely be entirely made of silicon, with the space of the present SCT largely taken up by detectors with much shorter strips. Several large-scale R&D projects on the sensors and module concepts for this upgrade are running, including sensor and module prototyping. We will report upon the commissioning experience from the SCT, use it to extract valuable lessons for future silicon tracker projects, and give an up-to-date overview of the status and results of the R&D efforts for the ATLAS tracker upgrade.


Introduction
The CERN Large Hadron Collider (LHC) is a protonproton collider designed for a center of mass energy of √ s = 14 TeV and an instantaneous luminosity of 10 34 cm −2 s −1 . ATLAS is one of two general-purpose detectors currently being commissioned at the LHC [1]. The ATLAS Inner Detector is responsible for reconstructing tracks and contributing to particle identification [2,3]. As shown in   1, it consists of three subdetectors, all within a 2 T magnetic field provided by the superconducting Central Solenoid magnet. Closest to the beam line are the pixel detectors for precise spatial measurements and vertexing. Next comes the Semiconductor Tracker (SCT), the subject of this paper. And outside the SCT is the Transition Radiation Tracker (TRT), which uses gas-filled straw tubes for tracking and fibers or foils to provide transition radiation for electron identification. TRT(end-cap) 1

The Semiconductor Tracker
The SCT is a silicon microstrip tracker, made up of four barrels and eighteen end-cap disks, nine per end-cap. Figure 1 shows the layout, with the barrels located at a radius of 299 mm to 514 mm, and the disks located at z = ±854mm to z = ±2720 mm. Placed on the disks and barrels are modules holding p-in-n single-sided microstrip sensors. The modules need to be able to withstand a dose of 2 × 10 14 1 MeV-neutron-equivalent/cm 2 , which would account for the first ten years of running of the LHC with a 50% additional safety factor. Figure 2 shows a diagram of a barrel module [4], 2112 of which are placed on the four barrels. Each module contains four microstrip sensors made by Hamamatsu [5], 64 mm in length and width, 285 µm thick, with AC-coupled strips of 80 µm pitch. Pairs of sensors are attached end-to-end, resulting in 768 strips of 126 mm in length per pair. A module contains two pairs of sensors, one on each side, with a relative stereo angle of 40 mrad. Figure 3 shows photographs of the three types of modules used in the end-caps [6], outer, middle, and inner, based on whether they are part of the outer, middle or inner ring of modules on the disk. There are 1976 modules total in the two end-caps. Due to the shape of the sensors, the pitch of the strips is variable, ranging from 57 µm to 94 µm. Like the barrel modules, the outer and middle (except on Disk 8) modules are made of four sensors, with two sensors attached end-to-end on each side, resulting in strips about 12 cm long. A pair of sensors is placed on each sides of a module, with a relative stereo angle of 40 mrad between them. The inner modules, as well as a variant of the middle modules used in Disk 8, only use a single sensor on each side, again with a stereo angle. The sensors were manufactured by Hamamatsu [5] and CiS [7]. A Cu/polyimide hybrid flex circuit holds twelve ABCD3TA ASICs [8], fabricated using DMILL technology for radiation hardness, to read out the strips. Each chip reads out 128 channels, so six are placed on each side of the module on the hybrid to read the 768 strips for the sensors on that side. The ASICs implement a binary readout scheme, meaning that there is either a hit for a strip or not. Thus, choosing the appropriate threshold is key: too low, occupancy will increase; too high, efficiency will decrease. The specifications require a noise occupancy below 5 × 10 −4 with a detector efficiency greater than 99%. Figure 4 shows that this is possible even after irradiation. The nominal threshold is 1 fC, and the green bands in the right plot show the range of thresholds for which the requirements would still be met. The ABCD3TA allows for known charges to be inserted to the readout for calibration, and the threshold settings can be trimmed per channel.
Communication for the data acquisition system (DAQ) is optical, with one fiber for clock and commands to the module and two for readout from the module. The communication is made to be fault-tolerant. On the hybrid, bad ABDC3TA ASICs can be bypassed. If the input signal path is broken, clock and control can be taken from a neighboring module, and for a broken output path, most of the data can be routed to the other of the two fibers.
Power is supplied individually to each module from floating power supplies. There is a high voltage power supply to bias the sensors, with a range from 0 to 500 V. The initial operating voltage will be 150 V, but it will need to be increased after the sensors suffer radiation damage. Low voltage power supplies provide analog power, digital power, and power to the PIN diodes and VCSELs used to receive and send data along the fibers. The power system is monitored and controlled using a Supervisory Control and Data Acquisition (SCADA) system based on PVSS-II from ETM [9] and a finite state machine (FSM).
In order to limit the reverse annealing of the sensors, the temperature needs to be kept at around −7 C. This is accomplished with an evaporative cooling system that uses C 3 F 8 [10]. The detector is filled with dry N 2 gas to prevent condensation and because it is inert. The humidity is monitored using radiation-hard Xeritron sensors, along with non-radiation-hard Honeywell sensors for studies and monitoring during early running, interfaced to the PVSS-II based SCADA system. The temperature of the modules, of the cooling loops through which the C 3 F 8 flows, of the gas, and of the mechanical structure are similarly monitored using NTCs. In addition to software interlocks and monitoring provided by PVSS-II and the FSM, there is a hardware-based interlock system that cuts the power of the modules on a cooling loop if the temperature is measured to be outside a certain range.

SCT Commissioning
The sensors were tested by the manufacturer, and they were checked upon reception on a sampling basis. The modules were assembled at various locations, being put through an extensive suite of tests at various times in the production sequence. The performance of both irradiated and nonirradiated modules was evaluated in beam-tests [11], an example of which was given in Fig. 4.
Between June 2004 and August 2005 the barrel modules were mounted on carbon-fiber barrel structures using robots, and the four completed barrels were shipped to CERN. Similarly, modules were mounted on the endcap disks, with the completed disks being sent to CERN. In a surface building at CERN, the SCT assemblies were placed inside the corresponding TRT assemblies, and combined SCT and TRT tests were performed [12]. Then in August 2006, the SCT+TRT barrel detectors were installed as one package in the ATLAS cavern, with continuity checks and a sign-off taking place in April and May 2007. The SCT+TRT end-cap assemblies were installed in the cavern in May and June 2007, with sign-offs coming in January and February 2008.
Subsequently, the SCT was run combined with the TRT, and the SCT barrel was run together with much of the rest of ATLAS in Milestone week 6 (M6) in March 2008. After that, inner detector commissioning focused on signing off the pixel detectors that, along with some problems encountered with the cooling system, resulted in a few months during which the SCT was not run. Work on the SCT during that time continued, consisting of developing the software and other things that did not require cooling the detector.
Finally, on 12 August 2008, the SCT started running again, with an aggressive schedule to be prepared for the planned LHC turn-on set for 10 September 2008. An initial task was to test cooling the full detector stably. All but two cooling loops, one to Quadrant 2, Disk 9 and one to Quadrant 1, Disk 1, both of End-cap C, are presently running. Another early task was to configure the optical communication to the modules, including setting redundant mode correctly where there are problems. The discriminator thresholds also needed to be tuned. One problem recently encountered is a high rate of deaths of the VCSELs used to transmit commands and clock to the modules. The suspected culprit is ESD damage during the handling of the optical hardware. Luckily these VCSELs are located in crates in the service caverns so they can be replaced.
A common task in many sensor tests is the threshold scan. For a given charge injection value, a threshold scan repeatedly injects the charge and reads if there was a hit using a range of discriminator thresholds. This hit efficiency versus threshold is fit with a complementary error function. From plotting the discriminator thresholds at which the hit efficiency is 50% as a function of the injected charge, the gain of the channel can be determined. From the width of the turn-off of the complementary error function, the noise can be determined, and this can be divided by the gain to determine the equivalent noise charge (ENC). Plots of the ENC for End-cap C measured during the sign-off are given in Fig. 5. Note that these are for warm running (around 25 C); there is less noise when the modules are cooled. Endcap A shows similar behavior, and the barrel modules show similar behavior to the long end-cap strips. For comparison, a MIP is expected to deposit a charge of 3.6 fC.
In addition to measuring module performance, combined running has been useful to set up the timing and test the DAQ system. It is also useful to test the offline software, monitoring, reconstruction. Finally, cosmics have been used for alignment. This was performed during the surface tests, and also during the M6 running, though statistics for that were lower.

The Super LHC
The Super LHC (SLHC), planned to start in 2018, will have a peak luminosity ten times that of the LHC. The TRT would have too high of an occupancy, and increased SCT occupancy would also degrade performance. The SCT and pixel detectors would have also suffered radiation damage by then. Therefore, a new inner detector is need [13]. The current plan is for an all-silicon system, in the barrel consisting of four pixel layers, three layers of short strips, 25 to 35 mm in length, and two layers of long strips 90 to 120 mm in length. Figure 6 shows the current straw-man proposal. For radiation hardness, the proposal is to use n-in-p sensors. Test sensors have been built.
The plan is to combine multiple modules into a supermodule or stave, shown in Fig. 7, instead of installing the individual modules onto the barrel, as was done in the SCT. This will allow for simpler assembly with more work going on in parallel, and it will potentially make it easier to replace faulty modules. The power distribution system will also have to be updated. The current independent power scheme, where each module has its own power supplies, does not scale enough for the SLHC. One potential scheme is to have serial power, where the modules are connected in series, with each module stepping down the voltage. A prototype was built that supplies 30 hybrids with 4 V each by providing 120 V to the chain. Another scheme, DC-DC conversion, increases efficiency by sending higher voltage, which needs to be stepped down at the module. For high voltage distribution, options include decreasing granularity and allowing for faulty sensors to be bypassed, and local high voltage generation with a step-up transformer.
The front end electronics have to be upgraded to support the new n-in-p sensors, as well as to upgrade from the now old DMILL technology. Therefore, a new deep sub-micron front-end ASIC, called the ABCn, has been designed and submitted for fabrication, with engineering samples expected in October 2008. The final design should be in 0.13 µm technology, although 0.25 µm technology has been used for prototyping. A binary readout is maintained. The communication bandwidth has been increased, and the various proposed power distribution schemes are supported.
The cooling capacity will also have to be increased. The current proposal is to use CO 2 cooling, though other options are also being considered.

Conclusion
The LHC is currently getting started. The SCT is ready to take part in the initial running, as a result of many years of work by many people. The commissioning is continuing, with the running of the detector being tuned, and much effort continuing to be spent to make sure that the data taken by the detector can be used to enable the physics goals of the ATLAS experiment.
There have been yearly workshops working on the upgrade starting from 2005. Ten countries are working on the upgrade of the tracker. Even though the LHC is just now starting, considering that it is planned to install the upgrade in 2016 to 2018, the schedule is very tight.