Status of the Timepix MCP-HPD development

This paper describes the design of a high-speed, single-photon sensitive, Hybrid Photon Detector (HPD). The detector consists of a vacuum tube, containing a Micro Channel Plate (MCP) and 4 CMOS pixel readout chips, sealed with a transparent optical input window with a photocathode. The design described here utilizes currently available technologies, specifically the Timepix readout chips and the Photonis Planacon MCP-PMT vacuum tubes. The aim of the project is to demonstrate the feasibility of a 4-side buttable square MCP-HPD with high packing fraction sensitive area. Presented here is the mechanical and thermal design of the prototype detector.


Introduction
The Medipix2 collaboration (www.cern.ch/medipix) has recently started the development of a Micro Channel Plate -Hybrid Photon Detector (MCP-HPD) prototype based on the concept previously described by Vallerga et al [1]. The MCP-HPD consists of a vacuum tube housing, a MCP and a pixel read out chip, sealed with a transparent optical input window having a photocathode coating.
The operating principle of a MCP-HPD is the following: A photon hitting the photocathode ejects a photoelectron into a drift electric field, which transports the incident electrons onto the MCP. The MCP is a glass plate with an array of miniature pores and electrodes on both surfaces for biasing. The pore walls have a high secondary electron emission coefficient and thus, when photoelectrons enter the pores of a biased MCP, they are accelerated and hit the walls releasing secondary electrons. This causes an avalanche effect resulting in a cloud of electrons exiting from the rear surface. Finally, the released electron cloud is carried by another drift field onto the input pad of the bare pixel readout chip where it is sensed as a charge pulse by the readout electronics.
The potential benefits of the MCP-HPD detector compared to conventional MCP-PMTs are the much higher pixel count and therefore increased spatial resolution and the use of smaller MCP gains due to the more sensitive detector. Decreased gain will directly increase the lifetime of the MCP. Compared to HPDs, MCP-HPDs are significantly smaller, are less sensitive to magnetic fields and require much less bias high voltage.
The aim of the prototype development is to extend the previously presented concept to a rectangular 4-side tileable MCP-HPD, which allows large areas to be covered with a high active area fraction. Existing components and technologies have been utilized as much as possible in the design of the prototype detector.

Detector platform
The prototype tube design is based on a Photonis Planacon 80512 MCP-Photon Multiplier Tube (MCP-PMT) vacuum tube body shown in figure 1. The tube dimensions are 58 mm x 58 mm x 13.7 mm and it has a very good open area fraction of ∼75 %. The Planacon tube body is constructed of interleaved ceramic and metal rings and a ceramic anode plate that are brazed together to form a vacuum tight body. The optical input window and the MCP are mounted on the metal rings, which provide bias voltages to the photocathode and to the MCP as well as activation currents for the getter pumps placed inside the tube. The selected MCP configuration is a chevron-type stack of two MCPs, with a pore size of 25 µm and an L/D (Length to Diameter) ratio of 40:1. Photonis offers a large selection of photocathode materials, of which the UV sensitive SE20-UV was selected for the prototype.

Prototype design
To allow the integration of 4 Timepix chips into the Planacon tube the ceramic anode plate is replaced with a custom designed one. The multilayer ceramic board provides vacuum feed throughs for the readout chip I/O signals. The same technology has been used previously in LHCb RICH HPDs [2]. The Pin Grid Array (PGA) connection of the I/O output signals on the back side are arranged around the perimeter to fit into a Socket 7 Zero Insertion Force (ZIF) socket. The socket has a 28 mm x 28mm opening in the middle, directly under the read out chips, to allow the attachment of a heat sink or a cooling element.
In addition to the custom anode plate, some modifications to the tube had to be made to adjust the gap between photocathode and the MCP (cathode gap) as well as the gap between the MCP and the Timepix chips (anode gap). The cathode gap is directly and inversely proportional to the spatial resolution achievable. In order to take advantage of the excellent spatial resolution of the Timepix chips (55 micron pixels) it has to be reduced to minimum. A conservative target gap of 0.5 mm was selected for the prototype to reduce the likelihood of short circuits. The target for the anode gap was also set to 0.5 mm. With such a gap the electron cloud exiting the MCP will spread -2 -

JINST 5 C12020
Ceramic board MCP   over a number of pixels. By calculating the centre location of the charge spread, sub-pixel position accuracy can be achieved. As experience of assembly and machining tolerances is gained with this prototype, it is hoped that the anode and cathode gaps can be further optimized to improve the achievable spatial imaging resolution.
Without a major re-design of the tube, the cathode gap can only be reduced to the target value of 0.5 mm by switching from a flat input window to a step-down input window (figure 2.) and therefore this approach was selected. The current plan to reduce the anode gap is to insert a ∼2.3 mm thick spacer underneath the Timepix chips to lift them closer to the MCP. The introduction of such a thick spacer creates challenges for the wire bonding and obviously increases the thermal resistance between the chips and the cooling unit. However, since this approach allows the use of the original tube body and a simple flat ceramic back plate, it involves less risk than other options.

Thermal design considerations
The optical input window is attached to the tube body with an indium alloy seal, which has melting point in the range of 100-150 • C, depending on the exact alloy that is used. In order maintain the integrity of the indium seal, Photonis specifies a maximum operating and storage temperature of 50 • C for the Planacon tube. When in operation, 4 Timepix chips output up to 4 watts of heat, which could raise the temperature of the tube enough to compromise the reliability of the indium seal and subsequently the vacuum inside the tube. Thermal simulations were done to investigate the need of cooling and how it could be efficiently implemented in the design.
A block model of the detector was created for the thermal simulations. The model contains 7 parts: Quartz window, Metallic frame, Ceramic frame, Ceramic board, Spacer/chip adhesive, Chip and Heat sink. To simplify the model, the multiple ceramic and metallic frames that construct the tube walls (figure 2) have been modelled as two frames and the four Timepix chips as a 1 large chip. The modelled heat sink (28 x 28 x 1 mm) has an equivalent thermal resistance of a 10mm thick copper block, which should be tall enough to allow attachment of external cooling unit below the adapter board.
-3 - The thermal simulations were done with ANSYS and set up as follows. Scenario A, no cooling: 4 watt heat flow in to the chip surface, radiation and convection out from the outer surfaces, except from the bottom surface. Scenario B, with cooling: same configuration as Scenario A, with a fixed temperature of 20 • C defined for the bottom surface of the heat sink to model cooling (infinite cooling power). The ambient temperature was set to 20 • C. Convection and radiation loss from the bottom surface was neglected, since it was estimated to be very small in the final configuration, due to the close proximity of the connector and the adapter board. Convection was modelled separately for horizontal and vertical surfaces. Temperature (surface) dependent convection coefficients were calculated for both cases. The radiation loss through the sides and the top surface was modelled with an emissivity coefficient of 0.9. At this stage the radiation from surface to surface inside the tube was neglected to simplify the simulations. Figure 3a and 3b show the results of the thermal simulations for both scenarios, with and without cooling. According to the simulations the temperature of the interface between the input window and the tube body, where the low melting point Indium seal is located, rises to over 65 • C, if no cooling is applied. In real life the tube will always be used in a closed environment that heats up with the detector. This will result even higher temperatures at the Indium joint location. Thus it can be concluded that active cooling is required to extract the heat generated by the Timepix chips, so that the detector (and its surroundings) won't overheat and compromise the seal and the tube vacuum.
The results shown in figure 3b represent a scenario where a cooling system, such as water/liquid cooling (infinite power, inlet temperature 20 • C) is connected to the back of the heat sink. Because of the close proximity and good thermal contact between the heat source (chip surface) and the cooling unit, the temperature of the whole package remains close to the temperature of the cooling unit. Location of the cooling, just underneath the chips, is an effective way to cool the entire detector and to ensure its reliable operation.

Mechanical design considerations
The tube body assembly including back plate attachment by brazing as well as the input window sealing will be provided by Photonis. The Medipix design group is responsible for the ceramic back plate design and the chip attachment and therefore only the issues related to that work are covered here. The current plan to attach the spacer and the chips onto the ceramic board is to use a low outgassing glass-silver adhesive. As mentioned earlier, the prototype detector will have a target anode gap of 0.5 mm. To achieve a good imaging performance the anode gap as well as the planarity of the 4 Timepix chip surfaces has to be well controlled. This will require very good control of the chip and spacer bond line thickness as well as the die bonding procedure. Tests and prototyping with blank pieces of silicon and ceramics are needed to define the tolerances of the chip and spacer bond line thickness.
In addition to the tolerances in the assembly procedures the bow of the ceramic plate due to the pressure difference has an effect to the anode gap. Simulations for a 1 mm thick blank ceramic plate were done to define the magnitude of the ceramic plate bow. According to the results, the maximum displacement was ∼20 µm. The spacer and heat sink attachment will make the ceramic plate even more rigid and thus reduce the displacement. The bow of the ceramic plate can therefore be regarded as insignificant, at least in this prototype design.

Tube production and assembly plan
The ceramic plate manufacturing as well as PGA pin attachment will be done by Kyocera. The PGA pins are attached by brazing at ∼1100 • C, so that they withstand the subsequent assembly step, where all the tube body parts are brazed together at ∼800 • C. The tube housing subassembly will be brazed together at Photonis and the parts will then be sent to CERN for spacer and chip attachment. Low outgassing silver-glass adhesive was selected to be used for the spacer and chip attachment. The spacer material candidates include ceramics, such as Aluminum oxide and Aluminum Nitride (AIN) or CTE matched metal alloys, such as Copper-Tungsten (CuW), which is a heat sink material commonly used with ceramics. The spacer and die attachment procedure will be first tested with blank pieces of silicon and ceramics/metal to determine the chip positioning accuracy, bond height tolerance and to measure the outgassing of these test assemblies. The wire bonding into the sub assembly will be done at NIKHEF with their deep access bonding machines. Gold ball bonding will be used because of their expected better reliability after being exposed to high temperature in the subsequent tube assembly steps. The subassemblies will be then electrically tested before being sent to Photonis. Photonis will mount the MCPs inside the subassemblies and pre-treat them. The subassembly will then be vacuum baked at ∼300 • C and finally sealed with the optical input window that has the photocathode coating.