CERN Accelerating science

ATLAS Note
Report number	ATL-UPGRADE-PROC-2012-001
Title	The FE-I4 Pixel Readout Chip and the IBL Module
Author(s)	Barbero, M (U. Bonn (main))
Corporate Author(s)	The ATLAS collaboration
Publication	2012
Imprint	12 Jan 2012
Number of pages	10
In:	International Workshop on Vertex Detectors , Rust, Austria, 19 - 24 Jun 2011
Subject category	Detectors and Experimental Techniques
Accelerator/Facility, Experiment	CERN LHC ; ATLAS
Free keywords	FE-I4 ; IBL ; pixel
Abstract	FE-I4 is the new ATLAS pixel readout chip for the upgraded ATLAS pixel detector. Designed in a CMOS 130 nm feature size process, the IC is able to withstand higher radiation levels compared to the present generation of ATLAS pixel Front-End FE-I3, and can also cope with higher hit rate. It is thus suitable for intermediate radii pixel detector layers in the High Luminosity LHC environment, but also for the inserted layer at 3.3 cm known as the “Insertable B-Layer” project (IBL), at a shorter timescale. In this paper, an introduction to the FE-I4 will be given, focusing on test results from the first full size FE-I4A prototype which has been available since fall 2010. The IBL project will be introduced, with particular emphasis on the FE-I4-based module concept.
Copyright/License	Preprint: (License: CC-BY-4.0)

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