FTK: a Fast Track Trigger for ATLAS

We describe the design and expected performance of a the Fast Tracker Trigger (FTK) system for the ATLAS detector at the Large Hadron Collider. The FTK is a highly parallel hardware system designed to operate at the Level 1 trigger output rate. It is designed to provide global tracks reconstructed in the inner detector with resolution comparable to the full offline reconstruction as input of the Level 2 trigger processing. The hardware system is based on associative memories for pattern recognition and fast FPGAs for track reconstruction. The FTK is expected to dramatically improve the performance of track based isolation and b-tagging with little to no dependencies of pile-up interactions.

will be upgraded by installation of an additional Pixel Detector layer. The new layer will be inserted between the B-layer of the existing pixel detector and a new smaller radius beam-pipe. The SCT system consists of 4 double layer of silicon strip detectors. Each double layer has an axialand a stereo layer with 80 µm pitch, oriented along the beam direction (axial) in one layer and tilted by 40 mrad angle (stereo) in the second one. The entire SCT has 6M channels and consists of cylinders at radii of 30.0, 37.3, 44.7, and 52.0 cm. The end-cap modules are very similar in construction but use tapered strips aligned radially. The FTK uses all 3 Pixel and 4 SCT double layers mapped into 11 logical layers. Use of the insertable B-layer is anticipated, too. The rapidity coverage extends up to |η| < 2.5. Details regarding the inner detector are given in ref. [2].
A three level trigger system [3] is used to select interesting events. The first level is hardwarebased, operating at a maximum output rate of 100 kHz. It provides regions of interest, portions of the detector in azimuth and pseudorapidity, which causes the event to trigger. Level 2 and the Event Filter are build by using computing farms and are collectively known as the High Level Trigger (HLT). The HLT consists of several thousand CPUs. Level 2 operates within regions of interest with an output rate of 2 kHz, while the Event Filter has access to all information in the event, with an output rate of 200 Hz.
2 Technical design 2.1 Overview The FTK system core design is based on the experience of the Silicon Vertex Trigger at the CDF detector at Fermilab [7,8]. The system is based on FPGAs and a highly-parallel Associative Memory (AM) chip [9]. The system is divided into eight core crates, each covering a 45 • range in azimuth plus 10 • overlap. Each core crate is further divided into four regions of η and two regions in φ . This yields 8 η −φ towers per crate and 64 trigger towers altogether. A η −φ tower is served by two processing units containing the AM chips for pattern recognition, Track Fitters (TF), Data Organizers (DO) to coordinate between pattern recognition and track fitting, and a Hit Warrior (HW) to remove duplicate tracks from the output. The processing units receive inputs from Data Formatter (DF) boards and pass their output to second stage boards which perform final full resolution track fitting and quality tests. Each of these components are described below. A sketch is given in figure 1.
Dual output front end links (RODs in figure 1) from the silicon detectors direct a duplicate set of the output to the Data Formatter boards which perform hit clustering and formatting of the data to be mapped to the 11 logical layers of the FTK architecture. Then it routes the clusters to the relevant processing units. In each processing unit the Data Organizer reduces the cluster resolution by a factor ≈ 10 into superstrips used for pattern recognition while storing the full resolution clusters for track fitting. The superstrips then are passed to the AM chips. Those operate in parallel to compare the incoming superstrips to approximately 100 million precomputed patterns per core crate. Matched patterns are sent back to the DO, which retrieves the full resolution hits and sends them to the Track Fitter. The TF does linear calculations of the helix parameters and χ 2 components using prestored constants and the location of the hit in each layer. Every combination of hits within a given pattern is fitted; those passing a fit-quality criteria are kept. The last stage of each processing unit is the Hit Warrior which removes duplicate tracks based on the number of shared hits between various tracks and the χ 2 of the fit.

Pattern recognition and track fitting
FTK tracking is performed in two stages to keep the combinatorics at a manageable level. The first stage uses 8 out of 11 silicon layers for pattern recognition and track fitting while the second stage refits the tracks found in the first stage using all 11 layers. The first 8 layer stage uses 3 Pixel, 4 axial SCT and 1 stereo SCT layer. At least seven of eight layers are required to have a hit. The pattern matching takes places in CAM-based custom built AM chips, each containing 50k-100k patterns each. Hits entering the system are simultaneously compared to all stored patterns. The AM chips are grouped in sets of 32 chips on a local associative memory board (LAMB). Each AM board contains four LAMBs. Once all matched patterns, called roads, in an event are found the information is sent back to the DO. The DOs are located on an auxiliary (AUX) card attached to the AM board. Each AUX card has four instances of the Data Organizer, Track Fitter and Hit Warrior. Upon receiving the roads from a LAMB, the Data Organizer looks up the full resolution hits within a road and sends them to the Track Fitter. The TF unit is expected to fit one track per nanosecond. This high rate is achieved by the large numbers of DSPs in the FPGA used to perform a simple linear fit for each set of N hit coordinates x j : The p i are the five helix parameters and the N − 5 χ 2 components, all of which are determined from the constants c i j and q j . If a fit is above a given χ 2 threshold and the candidate track has hits in all the detector layers, a majority recovery is performed. During this recovery the track is refitted several times, ignoring one of the hits each time to check whether a subset of hits will yield a good χ 2 . This allows a track to be recovered if one of the hits in the combination comes from noise or from a different track. The second stage of fitting uses the good tracks from the first stage to look for expected hits in the remaining 3 layers, using an inversion of eq. (2.1). If at least 10 out of 11 hits are found, the track is refit with all of the hits and subjected to a final fit quality test. The tracking process takes in average about 15 µsec.

Variable resolution patterns
One of the challenges in the design of the FTK is the large number of matched roads expected at 3 × 10 34 cm 2 /s. Although the system is already segmented into independently operating η − φ towers, the number of matched roads out of the AM could still be a challenge for the Data Organizer at very high instant luminosities and better pattern matching resolution could be necessary. Variableresolution patterns have been developed to obtain better resolutions with equal AM bank sizes or the same resolution with much smaller banks [10]. Finer-resolution patterns lead to a lower fake rate at the cost of more required AM space, while coarse resolution maintains higher efficiency at the cost of increased combinatorics in the Track Fitter. The solution described here maintains a balance between these considerations. The logic of the AM chip design has been upgraded to include local subdivisions of each superstrip in a pattern.
The "don't care" feature of modern CAMs is implemented so that the width of each pattern can be varied layer by layer. This allows the available hardware pattern space to be optimized to maximize efficiency while minimizing the number of random hits that have to be fit.
Simulation studying events with different pile-up conditions have been performed. A standard AM bank produces roughly the same number of roads of a variable resolution pattern bank that is 3-5 times smaller when using a single DC bit in the AM logic [10]. At the level of 70 pile-up, a fairly uniform 900-1300 clusters are expected per layer and tower.

Physics with the FTK
There is a variety of physics applications for the FTK. One of the most prominent is the source of electroweak symmetry breaking which remains yet unknown. The easiest explanation, the Higgs mechanism [4][5][6], predicts the Higgs boson whose branching ratios to other particles are dependent on the their masses. Therefore the production of heavy particles like b-quarks and τ leptons are of particular interest. These couplings can be modified by new physics and their measurement is a crucial test for the Standard Model. We will show that particuarly for these final states the FTK system leads to significant improvements. In Standard Model measurements the FTK helps to maintain high efficiencies while controlling background processes at high pile-up. Figure 2, left, shows the isolated muon efficiency using the EM calorimeter isolation with two different cell energy thresholds as function of the number of pile-up interactions. The selection criteria are chosen such that the bb rejection factor is 10. The second plot of the same figure demonstrates that by applying tracking isolation in contrast to calorimeter isolation the efficiency improves. Considering only tracks from the muon vertex by applying a selection criteria on the distance between muon and track at the beamline track the efficiency becomes largely independent of the pile-up. These examples demonstrate that tracking can play an important role in identification of interesting events while maintaining high efficiency. With increasing luminosity the use of tracking increases even more. The FTK will operate at the Level 1 trigger output rate, reconstructing all tracks at near-offline quality for use in the HLT. In addition this frees up CPU time in the HLT, which can be used for other purposes.

Simulated performance
The FTK system has been simulated in software to determine its expected performance [1]. Tracks provided by the FTK system are compared with tracks reconstructed using the ATLAS offline tracking algorithm. The resolution of track parameters is shown in figure 3 for tracks with |η| < 1, demonstrating that the FTK resolution is comparable to that of the offline tracking. The FTK configuration uses collections of pre-calculated pattern (pattern banks) and linearized fitting constants suitable for up to 75 pile-up interactions. Figure 4 shows the efficiency of the FTK and offline algorithm to reconstruct muons of p T > 1 GeV. The efficiency drops for FTK tracks around pseudorapidity η = 1 are located at the transition region between barrel detector and forward disks. These have been addressed by relaxing the number of hits required in these particular regions.
The potential for heavy flavor identification (b-tagging) with the FTK tracks at high luminosities is evaluated using an algorithm based on the transverse impact parameter d0 of tracks in jets. Template histograms of the impact parameter divided by its uncertainty are created for light jets and b jets. These are combined to form a likelihood. Figure 5 shows the expected b-quark efficiency along with typical light jet rejection factor for FTK and offline tracks. Simulated event samples are W H → bb. Typical b-tagging efficiencies used in analyses are ∼ 0.5-0.7%.

Conclusion
The Fast Track Trigger for ATLAS will be able to increase efficiency and control background processes for particularly interesting events containing b quarks, τ leptons and isolated, high p T electrons and muons. This is achieved by using global, high speed tracking at the beginning of the -5 -  Figure 3. Comparison of the helix parameters for Offline track reconstruction (black) and FTK (red). The track's transverse momentum is required to exceed 1 GeV and its pseudorapidity is limited to the central region (|η| < 1). A single muon sample is used. Figure from   Level 2 trigger. The challenges given by increased combinatorics in track reconstruction with increasing luminosity and simultaneously greater need for computational power are solved by using precomputed AM based patterns and fast FPGAs in a highly parallel system.
A vertical slice test using collision data in summer 2012 is in preparation [11]. The dual output silicon detector front end cards needed are already installed in ATLAS . The full set of dual output cards for the final system is already produced. A data formatter prototype board is currently under design and will be ready by summer 2012. A prototype input mezzazine [12] is ready for the vertical slice test. The AM chip prototype (AMchip04) is expected by early summer 2012 and the design of the AM board (AMBFTK) is finished. An existing board (AMBslim5) [13] will be used for the vertical slice test. For the data organizer board a pre-prototype is available and will be used in high-speed testing. The second stage board which performs the full 11 layer fit is currently undergoing conceptual design and firmware development. We expect the system to be operational in the data taking period following the 2013-2014 shutdown.