Global design analysis for highly repeatable solid-state klystron modulators

This paper presents an analysis of the repeatability issue in the electrical-to-radio frequency conversion chains using pulsed klystrons. The focus is on the power electronics used in klystron modulators. Repeatability definition is presented and simulation results allow deriving important conclusions regarding the voltage repeatability harmonic content versus power electronics design directions. The trade-off between klystron modulator and low level RF controls is a key point for optimizing the global system repeatability performance.


INTRODUCTION
A new accelerator, the Compact Linear Collider (CLIC), is under study at CERN [1]. This accelerator requires a very tight specification in terms of Radio Frequency (RF) repeatability from the klystrons used to accelerate the drive beam. RF performances are directly linked to the quality of the High Voltage (HV) pulse produced by the klystron modulators as well as the Low Level RF (LLRF) control. Feed-back control loops are used to stabilise the modulator output pulsed voltage and to control the RF phase and amplitude. Figure 1 illustrates a simplified principle schematic of the power flows and the main control loops.
The modulator output voltage is typically characterised by a given harmonic content (ripple) and by some voltage stability. This can be translated into RF phase and amplitude undesired deviations. This issue has been analysed in [2]. A 10ppm to 50ppm HV pulse repeatability is preliminarily required from CLIC modulators. Being an extremely tight specification, one has to evaluate the trade-off between modulator voltage repeatability and LLRF control capabilities. LLRF feedback control can be used to attenuate the statistical effects of not perfectly repeatable voltage pulses (LLRF feedforward compensation being unable to comply with random perturbations). The LLRF control repeatability attenuation capability (in dB) is defined over a range of frequencies (Bode representation). This LLRF control characteristic shall be known in order to take important modulator design decisions, where the voltage repeatability harmonic content can be defined.
Before entering in a phase of global design optimisation, this paper aims to clearly define the pulsed voltage repeatability, identify the main sources of non-repeatability, and give a flavour of the expected voltage repeatability and its harmonic content for typical power electronics topologies used in a modern klystron modulator.

SOURCE OF NON-REPEATABILITY IN MODERN KLYSTRON MODULATORS
Modern klystron modulators are composed of power electronics sub-components (switch mode power converters). They offer the possibility of easily changing the voltage level, the pulse length, and to operate in feedback. The main power conversion concept based on power electronics is important for the following analyses and is illustrated in Figure 2, where a constant DC voltage can be efficiently converted into a variable, and controllable, one.

Switch
Filter DC Voltage A constant DC voltage V in is chopped by one or several controlled switches operating either in their "on" (conducting) or "off" (non-conducting) states at medium frequencies (typically 10kHz to 500kHz, depending on the modulator topology). The output voltage is obtained using power filters, which design must consider the trade-off between residual output ripple and bandwidth to produce a pulsed voltage [3].
When operating a switch mode power converter, switches are affected by a random turn-on and turn-off time jitter. At nano-scale, quantum physics and statistical physics drive the behaviour of charge carriers within switch semiconductor layers, and the jitter has a stochastic behaviour which can be described by a Gaussian distribution. As a consequence the output voltage of such power converters presents a stochastic behaviour with respect to the switch control signal. The nonrepeatability of a power converter may be affected by other phenomena such as temperature variations or electro-magnetic perturbations; however, it is assumed here that the major contributor is the switches jitter. Figure 3 illustrates a simplified visualization of the switch jitter impact on turn-on and turn-off time lags with respect to the switch control (from a driver). The hypothesis assumed in this work lies in the consideration of an instantaneous switch transition (0μs for turn on and off).

PULSE REPEATABILITY DEFINITION
In order to define the Pulse Repeatability (PR), the matrix V in equation (1) represents the voltage of a set of N pulses of length t f : is the voltage of the pulse i at the time t j .
Since switch jitter, and consequently the converter repeatability, is a stochastic phenomenon, there is no correlation between any pulses of a given set. Therefore, a set of N voltage samples for a given time t j (one column of the V matrix) can be seen as the realization of the random variable X tj of standard deviation σ Xtj . In practice, one can calculate the standard deviation σ tj of N voltage samples and approach σ Xtj by increasing the number of samples N. The higher the considered number of pulses and time samples, the higher the accuracy in estimating the repeatability.

REPEATABILITY TOLERANCE INTERVAL
The switch jitter induces Gaussian distributed voltage dispersion at each time t j (from t 1 to t f ) within the pulses as shown in Figure 5. A tolerance interval α which defines the probability for pulses to meet the repeatability specification such that the pulse repeatability at the time t j is PR tj =α.σ tj must be introduced. Table 1 shows the percentage of pulses which meet the specification for different values of α.

REPEATABILITY CALCULATION
At each time t j , the standard deviation σ tj of a set of X tj realization is derived from the columns of matrix V. Finally, the PR is obtained by multiplying the greatest σ tj obtained (worst case) by the tolerance interval α: This quantity is the maximum accepted voltage difference between any two pulses but it might be exceeded a certain percentage of time, defined by the tolerance interval.

TYPICAL POWER ELECTRONICS TOPOLOGIES IN KLYSTRON MODULATORS
Klystron modulator design requires an effort in finding the best compromises between voltage bandwidth (pulse rise/fall times) and ripple. To decrease the ripple amplitude, one can: 1) Reduce the filter band-pass: which also increases the pulse rise/fall times. 2) Increase the switching frequency: action limited by the switches technology and associated losses. A way of increasing the resulting output switching frequency of a power electronic converter consists in placing several parallel switching circuits (as illustrated in Figure 6(b)), operated in a phase shifted way (interleaved). With this solution the converter bandwidth (thus the rise/fall time) is conserved whereas the ripple is reduced. The equivalent switching frequency is given by f eq =n pc .f single where n pc is the number of parallel circuits, f eq and f single are the equivalent and the single circuit switching frequencies respectively). Topologies in Figure 6 are typically used in modulator subcomponents (e.g. the so-called active bouncer [5]).

SIMULATION RESULTS AND DISCUSSION
For the sake of simplification, suppose that topologies in Figure 6 are representing a very simplified klystron modulator, where R kly emulates the klystron equivalent resistance (for a given voltage) seen from the primary of the necessary high voltage pulse transformer. Illustrative simulations have been carried out for these two topologies operated with two different switching frequencies: 1) Single switch buck topology (Figure 6(a)) operated with f single =50kHz and f single =500kHz. 2) 5-phase interleaved buck topology (Figure 6(b)) operated with f single =10kHz and f single =100kHz.
For comparison purposes the output filter (L-C) is kept unchanged in all simulations which also allow keeping the same converter dynamics (voltage bandwidth). The considered main simulation parameters are listed in table 2. A magnification of the flat-top voltages produced by the two topologies for an equivalent switching frequency of 50kHz and 500kHz are presented in Figure 7(a) and 7(d) respectively. It is clear that keeping the equivalent, output, switching frequency but decreasing the single switching frequency using multiphase inerleaved topologies, improves the repeatability (PR on Figure 7(b) and 7(e)). However, it can be observed that for very high switching frequencies (500kHz), high frequency repeatability amplitudes decreases, as illustrated in Figure  7(d), 7(e) and 7(f). To analyse the frequency content of the PR, FFTs were performed and results are depicted in Figure  7(c) and 7(f). Finally, one can notice the following general tendencies; selecting lower switching frequencies, implies a wider spectrum of the repeatability function, whereas higher switching frequencies produce worse repeatability at lower frequency regions. The design decision of the klystron modulator highly depends upon the klystron's LLRF control. Likely, the LLRF feed-back control would be able to better compensate for lower frequency voltage repeatability phenomena, driving the design of the power electronics sub-modules toward the selection of higher switching frequencies.

CONCLUSION
The RF repeatability issue in the modulator-klystron conversion chain should be approached considering an integrated design of the power electronics systems and the LLRF controls. Depending on the LLRF controls capabilities, important design decisions can be taken for the modulator, such as the switching frequency and the power-electronics subcomponents topology. With higher equivalent switching frequencies of modulator sub-components, the repeatability harmonic spectrum shows important amplitudes in the low frequency region. This case seems to be preferable since the LLRF control could easily compensate the voltage repeatability phenomena in this frequency range. (e) f eq =500kHz (c) f eq =50kHz Multiphase (5) topology (f) f eq =500kHz