The phase-1 upgrade of the CMS pixel detector

The pixel detector of the CMS experiment will be upgraded during the extended end of year shutdown during winter 2016/2017. The upgraded detector will operate at full efficiency at an instantaneous luminosity of 2 × 1034 cm−2 s−1 with increased detector acceptance and additional redundancy for the tracking, while at the same time reducing the material budget. The design and technological choices will be reviewed, and the status of the construction of the detector and the performance of its components as measured in system tests are discussed.


Introduction
The Compact Muon Solenoid (CMS) experiment [1] is a general purpose detector at the CERN Large Hadron Collider (LHC) in Geneva, Switzerland. In order to reconstruct the different types of particles originating from the proton-proton (pp) collisions, the CMS experiment utilizes several subdetectors, such as an inner tracker, two calorimeters, and an outer muon tracker. The inner tracking detector [2,3] of the CMS experiment is made out of the pixel tracker and a strip detector. Prior to the upgrade, the pixel tracker was arranged in three barrel layers (BPIX) and two forward disks in each endcap (FPIX). It had been designed for the nominal instantaneous LHC luminosity of 1 × 10 34 cm −2 s −1 .
It was estimated several years ago that the LHC will exceed its design luminosity, and as a consequence the performance of the pixel detector will degrade because of dynamic inefficiency caused by data losses due to buffer overflows in the front-end read-out chips. In fact, during the 2016 pp collision runs of the LHC, a significant decrease of pixel hit efficiency in the first layer of the BPIX was observed, as shown in figure 1. For this reason the CMS collaboration built a replacement pixel detector [5], which was installed during the extended end-of-year shutdown during winter 2016/2017.
The so-called phase-1 upgrade of the CMS pixel detector was designed to operate efficiently up to instantaneous luminosities of 2 × 10 34 cm −2 s −1 . In order to achieve this, new read-out chips (ROCs) have been designed with larger buffer sizes and higher read-out bandwidth. Another major design change is a new layout of tracking layers: the innermost layer is brought closer to the beam line with a radial distance of 2.9 cm instead of 4.4 cm. Also, an additional tracking layer is introduced for both the barrel and forward regions. This will allow for better vertexing and tracking capabilities, but also adds redundancy. Even though a new tracking layer has been added to the detector, the passive material was significantly reduced due to a more compact mechanical support together with a new CO 2 cooling system, as well as moving services outside of the tracking volume. A pictorial comparison between the layout of the former and new pixel detectors is shown in figure 2. In the following, the upgrade is discussed in detail.

The new read-out chips and pixel module
The composition of a pixel module has not changed with respect to the former pixel detector: an array of ROCs (2 × 8 for the upgrade) is bump-bonded to an n + -in-n planar silicon sensor via lead bumps. On top, a thin printed circuit, the high density interconnect (HDI), is glued onto the sensor and wire-bonded to the ROCs. A token bit manager (TBM) is placed on the HDI and organizes the data stream of the ROCs. Each module is comprised of 66560 pixels, each with a size of 100 × 150 µm 2 . The pixel detector has a uniform module layout, which is a substantial simplification with respect to the former detector, that had seven different layouts for modules.

Readout chip and pixel detector modules
The readout chip of the upgrade detector, named psi46digv21respin, is based on the present psi46 readout chip [3]. The same process technology (250 nm CMOS) is employed in the new chip, as well as the zero-suppressed readout architecture based on the column drain mechanism. The chip readout is segmented into 4160 pixels, arranged in an array of 80 rows and 26 double-columns, covering an area of 102 ⇥ 79 mm 2 . Several important improvements are introduced in the upgrade -2 - The most important change of the pixel module's design is the new ROC. An 8-bit ADC and a phase-locked loop (PLL) have been added, allowing for a digitized read-out. Thus, the read-out speed has been increased from 40 MHz of the old ROC to 160 Mbits/s. The number of data and timestamp buffer cells is enlarged by at least a factor of 2 to total 80 and 24 buffer cells, respectively. With these two changes, the new pixel detector will overcome the inefficiencies mentioned in section 1. The ROC is designed to be radiation hard, allowing to operate the pixel detector until 2023, after which the detector will be upgraded again [6] to operate in the conditions of the high luminosity-LHC. Further improvements to the chip-internal cross-talk, the comparator and transistors reduce the noise of the chip und thus allow to operate the chip at a low threshold of about 1800 electrons.
The pixel modules in the innermost BPIX layer have to operate at high expected hit rates of up to 600 MHz/cm 2 . Therefore, a special version of the ROC [7] has been designed to handle these hit rates. The chip performs a dynamic cluster column drain where the hit data are transferred in clusters of 2×2 pixels to the buffer instead of the data of single pixels. Another difference for the pixel modules in the first BPIX layer is that two TBMs are placed on the HDI to organize the high-volume data stream of those ROCs.
In total, 1856 pixel modules were installed in the detector resulting in almost twice as many read-out channels as in the former detector (124 million pixels compared to 65 million pixels). They had to pass a rigorous testing procedure: the quality of the connections between different layers, i.e. the bump-bonds between ROCs and sensor and wire-bonds between ROCs and HDI, were tested after thermally stressing them. The high-rate performance of the ROC was measured using X-ray exposure. Further series of tests evaluated the quality of the pixels such as their noise properties or leakage current as a function of the applied bias voltage. The sum of these test results were used to discard modules of poor quality. Two examples of test results are given in figure 3.  The chip is > 99% efficient for hit rates expected at the LHC which is indicated by the red dotted line. Right: measurement of the pixel turn-on threshold for modules in the FPIX, in ADC units of test voltage setting (V cal unit = 50 e − ). The turn-on is measured after trimming the detector to a threshold of 35 V cal units. Grade A and B modules are of detector-quality, with A being the best quality. Grade C modules are discarded because of deficiencies, such as containing a significant fraction of pixels that are not trimable.

Commissioning of the
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Mechanical support and cooling
In figure 4, the mechanical structure of the pixel detector is shown. It supports the pixel modules and service electronics, while being of low mass to reduce particle interaction with passive material.  reconstruction, both offline and in the HLT. Missing energy reconstruction in the offline could also improved since "particle flow" has become an important tool in CMS. Good track reconstruction forms the foundation for the vast majority of our physics analyses, whatever they may be in the future.
In Figure 1.11, we see the expected tracking efficiency and fake rate of the upgraded pixel detector in various pile-up scenarios ( PU = 0, 50 and 100) in simulated tt events. The very large losses in efficiency with the current detector at high luminosities as seen in Figure 1.8 have largely been recovered. This leads to improvements in higher-level reconstructed objects like b-tagged jets, which can be seen in Figure 1.12. For example, the 15% absolute gain in efficiency for a fake rate of 1% translates into large gains in physics analyses that require more than one b-tag, such as the ZH ! µ + µ bb analysis discussed later. In addition to the gains in offline reconstruction, improvements in single track reconstruction play a beneficial role in the high-level trigger, when Level-1 objects are reconfirmed by tracks made from pixel hits alone. A gain in Higgs signal efficiency corresponds to greater sensitivity with the same amount of integrated luminosity.
Finally, besides improving pattern recognition, increasing efficiencies and lowering fake rates, the addition of the fourth outer layer of the new pixel detector plays another role. In the case that the inner layers of the TIB are compromised, the fourth layer largely offsets such losses, especially at high pile-up.

Changes since the Technical Proposal
Substantial progress has been made in specifying designs of the various components of the upgrade. The first version of the new ROC has been received from the fab, the CO 2 cooling system has been designed with prototypes in operation, the DC-DC power converters have The support structure is made out of a carbon fiber and Airex foam compound for BPIX, and carbon fiber and thermal pyrolitic graphite for FPIX. The pixel modules are held by support strips in the central part, and blades organized on half-disks for the forward part. These support strips and blades are highly thermally conductive, guiding the heat produced in the pixel modules to tubes containing the coolant.
The cooling system is based on bi-phase CO 2 as coolant instead of mono-phase liquid C 6 F 14 that had been used in the former detector. The heat of the detector is absorbed as latent heat of the CO 2 . The cooling system has a nominal operation temperature of -20 • C, which requires the CO 2 to be pressurized at about 20 bar. The tubes guiding the CO 2 are made out of stainless steel with an inner diameter of 1.6 mm and a wall thickness between 50 and 100 µm. They are embedded in the support structure.
Another significant difference in the mechanical design of the phase-1 and the former detector is that the service electronics for both the BPIX and FPIX pixel modules has been moved further away from the interaction point, thus greatly reducing the passive material within the tracking volume, as shown in figure 5.

Service electronics
Additional service electronics within the pixel detector is needed to be able to operate the detector.
The first class of electronics is DC-DC converter boards [8]. As the number of read-out channels is almost doubled with respect to the former detector, the power loss in the current detector would have been increased by a factor of about four. The power supplies would not have been able -4 -black points. Note that the "barrel outer tube" mentioned above and in Table 2. the material budget for both present and upgrade pixel detectors for the comp in Figure 2

Pattern Recognition and Track Reconstruction
The normal pattern recognition and track reconstruction use an iterative proc sisting of a number of steps where the idea is that better tracks are reconstructed hits removed before other tracks are reconstructed from the remaining hits. Th are those that are less likely to be fake tracks. Each of the tracking steps starts w of "seeds" formed from 2 (a pair seed) or 3 (a triplet seed) pixel hits consistent w mum track p T , and coming from some region of the beam spot. The first step us and higher minimum track p T , these are followed by steps using pair seeds an The later steps use seeds that contain or only consists of hits from the silicon s find detached tracks, e.g. from decay products of K 0 s mesons or L 0 baryons. presented in this chapter the later steps used to reconstruct detached tracks hav to speed up the reconstruction and reduce memory usage that can be an issue pileup scenario studied.
With the additional barrel layer and end cap disks, the upgraded pixel detector w lent four-hit coverage over its whole h range. This allows for the creation of fou to handle this amount of loss. Therefore, they are operated at a higher voltage (10 V) and lower current which reduces the power loss significantly. The on-detector DC-DC converters transform the high voltage currents to currents at low voltages (2.4 and 3.0 V for the analog and digital circuits of the pixel modules, respectively). The DC-DC converter boards are cooled with the same cooling circuits as the pixel modules.
The other class of service electronics located within the support structure of the detector aids the control and read-out of the pixel modules. Optical signals for clock and trigger pulses as well as configuration data are sent to the detector. They get converted into electric signals by digital opto-hybrids that are connected to printed circuit boards. Auxiliary chips synchronize the signals sent, translate them from the opto-hybrid's low voltage differential signaling (LVDS) to the TBM's low current differential signaling (LCDS) standard, and correctly distribute them to each individual module. Also, the jitter in these signals is filtered using a quartz crystal based PLL. The new pixel optohybrids [9] host linear laser drivers, level-translator chips, and transmitter optical subassemblies that convert the electric pixel hit data to light, which is sent out of the detector in optical fibers. For the two innermost BPIX layers, the pixel data are transmitted in four or two fibers per pixel module, respectively, while for all other layers, one read-out fiber per module is sufficient to transmit the data.
The data acquisition of the backend electronics for the upgraded detector is based on the µTCA standard with high-speed links of up to 10 Gbits/s. One class of boards, so-called front-end controllers, distribute the clock, trigger, and configuration signals, and the other class of boards, so-called front-end drivers, process the pixel hit data streams.

Status of the detector
The upgrade of the pixel detector was installed during the extended shutdown of the LHC during the winter of 2016/2017. All necessary calibrations were performed, and the detector was commissioned using both cosmic data and the first pp collision data of 2017. During the commissioning phase, -5 -

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the read-out chain had been exercised, and the detector was aligned both in time and space. More details can be found in [10]. Figure 6. The cluster occupancy for the pixel detector during the pp collision data run 297099. In the top row from left to right: the complete FPIX, BPIX layer 1 and layer 2; in the bottom row from left to right: BPIX layer 3 and layer 4. The cluster of non-functional modules in FPIX disk -1 has been recovered during later running. Taken from [11].
A snapshot of the cluster occupancy of the pixel detector is given in figure 6: in this figure, each module, a group of 16 ROCs, is indicated by a rectangle with a solid black boundary and the nominal ROC0 (the first ROC of the module receiving the read-out token of the TBM) is also indicated by a solid black border. For the FPIX (top left plot), the disks are displayed according to their z position of the CMS coordinate system1 along the horizontal axis with the inner disk being at smaller absolute values and outer disk at larger values. The half-disks with negative blade number are on the outer side of the experiment (i.e. with negative x position in the CMS coordinate system). For BPIX (other four plots), the layout is similar, the horizontal axis displays the z position of a module within a ladder, while the ladder position follows the same convention as the blade position for the FPIX. As the indices 0 are not used, each plot contains a white cross.
The snapshot of the cluster occupancy shows overall good quality, but three groups of pixel modules are non-functional: the empty clusters for pixel modules on disk +2 of FPIX and in the fourth layer of BPIX are non-functional due to issues with the corresponding read-out service electronics, while the cluster of pixels in the second and third layer of BPIX is due to an issue in a power group. Thus, the fraction of active pixels of 95.5% is lower than the > 98% of the former 1The x axis points radially inward toward the center of the LHC, the y axis points vertically upward, and the z axis points along the counter-clockwise beam direction [1].

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pixel detector. However, due to the increase in redundancy by having one additional layer, the impact on physics is expected to be negligible. Figure 7 shows the pixel hit efficiency for the upgraded pixel detector as a function of the instantaneous luminosity using 2017 pp collision data. It can be appreciated in comparison with figure 1 that the inefficiency observed for the innermost barrel layer of the former detector has been significantly decreased.

Summary
The phase-1 CMS pixel upgrade has been installed and commissioned in the beginning of 2017. The detector is successfully taking proton-proton collision data with a fraction of > 95% of pixels being active. Early studies have shown that the inefficiencies that were observed with the former detector are now largely reduced. The phase-1 pixel detector is expected to record collision data with high quality until 2023, after which it will be upgraded for the high luminosity-LHC.