Electronics performance of the ATLAS New Small Wheel Micromegas wedges at CERN

A series of upgrades are planned for the LHC accelerator to increase its instantaneous luminosity to 7.5 × 1034 cm−2s−1. The luminosity increase drastically impacts the ATLAS trigger and readout data rates. The present ATLAS small wheel muon detector will be replaced with a New Small Wheel (NSW) detector which is expected to be installed in the ATLAS underground cavern by the end of the Long Shutdown 2 of the LHC . With the final micromegas (MM) quadruplets (modules) already produced the activities concerning the integration of the modules into the final, fully equipped MM wedges, that will then be installed on the wheel structure on surface, are currently in full swing at CERN. One crucial part of the integration procedure concerns the installation, testing and validation of the on-detector electronics and readout chain for a very large system with more than 2.1 millions electronic channels in total. These include ∼4 thousands MM Front-End Boards (MMFE8), custom printed circuit boards each one housing eight 64-channel VMM Application Specific Integrated Circuits (ASICs) that interface with the ATLAS Trigger and Data Acquisition (TDAQ) system through ∼1 thousands data-driver cards (ADDC & L1DDC, respectively). The readout chain is based on optical link technology (GigaBit Transceiver links) connecting the back-end to the front-end electronics via the Front-End LInk eXchange (FELIX), a newly developed system that will serve as the next generation readout driver for ATLAS. Experience and performance results from the first large-scale electronics integration tests performed at CERN on final MM wedges, including system validation with cosmic-rays, are presented.

A : A series of upgrades are planned for the LHC accelerator to increase its instantaneous luminosity to 7.5 × 10 34 cm −2 s −1 . The luminosity increase drastically impacts the ATLAS trigger and readout data rates. The present ATLAS small wheel muon detector will be replaced with a New Small Wheel (NSW) detector which is expected to be installed in the ATLAS underground cavern by the end of the Long Shutdown 2 of the LHC. With the final micromegas (MM) quadruplets (modules) already produced the activities concerning the integration of the modules into the final, fully equipped MM wedges, that will then be installed on the wheel structure on surface, are currently in full swing at CERN. One crucial part of the integration procedure concerns the installation, testing and validation of the on-detector electronics and readout chain for a very large system with more than 2.1 millions electronic channels in total. These include ∼ 4 thousands MM Front-End Boards (MMFE8), custom printed circuit boards each one housing eight 64-channel VMM Application Specific Integrated Circuits (ASICs) that interface with the ATLAS Trigger and Data Acquisition (TDAQ) system through ∼ 1 thousands data-driver cards (ADDC & L1DDC, respectively). The readout chain is based on optical link technology (GigaBit Transceiver links) connecting the back-end to the front-end electronics via the Front-End LInk eXchange (FELIX), a newly developed system that will serve as the next generation readout driver for ATLAS. Experience and performance results from the first large-scale electronics integration tests performed at CERN on final MM wedges, including system validation with cosmic-rays, are presented.

Micromegas
A single Micromegas is a position-sensitive gaseous detector with planar parallel electrodes and consists of three planes: the cathode, the anode and the micromesh, as shown in figure 3. The mesh divides the gas volume between the anode (readout) and the cathode (drift) into two areas: the conversion/drift gap of 5 mm where the incident muon ionizes the gas molecules and creates primary electrons, and the amplification gap of 128 µm where electron avalanches occur. The anode plane is based on printed circuit boards (PCBs), with photo-lithographically etched copper strips and a layer of resistive strips on a kapton foil glued on the copper strips for the discharge protection.
The resistive strips have a resistivity of 10 to 20 MΩ/cm. The readout strips have a pitch of 450 µm.
The mesh is supported by 128 µm high pillars, which guarantee the uniformity of the amplification gap. The cathode is also a PCB having a copper surface. The resistive-strip Micromegas used in the upgrade of New Small Wheel features excellent spatial resolution (σ < 100 µm) irrespectively of the particle incidence angle, high detection efficiency even at the highest background rates, and good two-track separation. The very thin segmentation of the MM readouts (readout-strips), together with sufficiently good time resolution, can also be exploited to complement the TGC trigger system, adding to system stability and verification even as backups.

Electronics
A Micromegas double-wedge or sector combines 128 MMFE8, 16 ADDC, 16 L1DDC boards and 16 Low Voltage Distributor (LVDB) boards, as shown in figure 4. The MMFE8 is the frontend board which collects all the analog and trigger signals for the readout strips and houses the VMM [7] and Read-Out Controller (ROC) [8] chips. These muon-related-pulse data (charge and time measurements) are calculated by the chip within 200 ns and stored in its Level-0 (L0) buffers, to be selected by another electronic device at a later stage, namely, the ROC ASIC. The ROC is responsible for receiving the Level-0 Accept (L0A) signal from the back-end electronics of the ATLAS trigger and then forwarding this signal to the VMM. The L1DDC is the interface between multiple FE boards and the FELIX network interface. This is achieved using the high-speed serializer/deserializer GigaBit TransceiverX (GBTX) ASIC [9] developed at CERN. The GBTX is a radiation-tolerant ASIC fabricated using the IBM/GlobalFoundries 130 nm CMOS technology. The GBTX is capable of multiplexing a number of serial links (E-Links) to a single fiber. L1DDC provides also the clock and BC Reset (BCR) signals to the ADDC board. The ADDC receives the ART data (the address of the earliest strip) from 64 VMMs (eight MMFE8s). A priority-based hit selection is implemented in real time, and the selected data is sent to trigger processors. The LVDB provides low voltage power to MMFE8, L1DDC and ADDC boards.

Wedge electronics integration
The electronics integration of the Micromegas wedges takes place at CERN prior to the installation of the Micromegas sector on the NSW. The electronics integration is divided into three steps. The first step is the board and detector preparation and the cable testing, which includes the FEB standoff, grounding interconnections, cooling pad and zebra holders installation, and the cable integrity testing. The second step is the FEB integration and cabling, which includes the installation of FEBs and cabling and small-scale readout tests to validate board connectivity and noise. The third and final step is the sector readout test, which includes the electronics validation by the configuration and readout of the full Micromegas sector via High Voltage (HV) pulsing, VMM internal pulsing and cosmic rays.

Configuration path
For the configuration path, the various Micromegas boards are supplied with the GBT-SCA ASIC (Giga-Bit Transceiver -Slow Control Adapter) [10] which is part of the Gigabit Transceiver Link (GBT) chipset [11] and its purpose is to distribute control and monitoring signals to the front-end electronics embedded in the detectors. Also, the SCA provides a number of user-configurable electrical interface ports, able to perform concurrently at transfer operations. The user interface ports are: 1 SPI master, 16 independent I 2 C masters, 1 JTAG master and 32 general-purpose IO signals with individual programmable direction and interrupt generation functionality. It also includes 31 analog inputs multiplexed to a 12-bit Analog-to-Digital Converter (ADC) featuring offset calibration and gain correction as well as four analog output ports controlled by four independent 8-bit Digital-to-Analog Converter (DAC). The Micromegas electronics system is using the SCA chipset for three different applications: • Monitoring: perform the front-end monitoring of the various power and temperature sensors directly connected to the ADC channel of the SCA. The monitoring application is shown in the right part of figure 5.
• Configuration: perform the configuration of the ASIC chipsets which are placed on front-end boards using the SCA SPI and I 2 C masters.
• Calibration: perform the VMM calibration using an ADC channel of the SCA. The calibration procedure output plot of a MMFE8 can be seen in figure 5. An overview of the configuration/calibration/monitoring path is shown in figure 6.

Readout path
The main components of the readout path are the VMM and the ROC chipset. The VMM consists of 64 discrete channels and each channel connects to one Micromegas readout strip and performs charge amplification, discrimination and precise amplitude and timing measurements through ADCs. The VMM can provide a precise amplitude measurement of the input pulse encoded in a 10-bit word (PDO) and a precise timing estimation of the pulse's peak encoded in an 8-bit word (TDO). Shared among channels are the bias circuits, a temperature sensor, a test pulse generator, two 10-bit DACs for adjusting the thresholds and test pulse amplitudes, a mixed signal multiplexer, the control logic and the ART which consists of dedicated digital outputs (flag and address) for the earliest abovethreshold channel. The peak detector measures the peak amplitude and stores it in an analogue memory. The time detector measures the peak timing using time-to-amplitude converter (TAC). The data from up to eight VMMs are passed to the ROC ASIC that merges hits from the VMMs, reformats the data, adds headers and interfaces with the L1DDC. The data from the ROC are received by a GBT in L1DDC and sent via fiber to a general purpose network with a high-availability interface, called FELIX, as shown in figure 7. In the last step, the data which are available through FELIX and the general purpose network are collected through Software ReadOut Driver (SW ROD) applications and are packed up into architecture-defined ROOT [12] files. Initially, the first step of the readout path validation is the determination of the noisy and dead readout channels per MMFE8 using VMM internal pulser mode, as shown in figure 8. Boards with more than 5% noisy channels are replaced and noisy/dead lists per board are produced in order to proceed with the cosmic-ray data acquisition. The final step of the MM sector validation is performed with cosmic rays. The trigger is provided by scintillators at 100 Hz with full coverage along the precision coordinate covering partially the detector. For the Micromegas sector operation the nominal HV and gas settings are applied, +570 V for the strip channels, −300 V for the drift channels and the gas is Ar(93%) + CO 2 (7%).
Next, the data analysis of the muons which are produced by cosmic rays takes place. The analysis is focused on basic detector parameters like charge, cluster size, time distributions. The muon track reconstruction is performed analyzing the data collected in the eight layers of the Micromegas sector. The measured tracking efficiency is mostly defined by the chamber parameters (HV, gas etc.) but can also be used for validating the electronics complementary to the other tests, as shown in figure 9.

Trigger path
The ART signals from the VMM are driven to the ADDC that connects with up to eight MMFE8s (thus, 64 VMMs). The ART ASIC on the ADDC deserializes the ART addresses from several VMMs, appends a 5-bit VMM geographical address and a BCID timestamp. It then forms and  forwards a data packet to the MM Trigger Processor (TP) through optical fiber. A priority based hit selection is implemented in real time, and the selected data is sent to trigger processors. The basic idea for the ADDC is to use two customized ART ASICs to deserialize and align the 64 channels of ART data (32 channels for each ART) and complete the hit selection processing. After the hit selection processing is finished, the selected data from each ART ASIC are sent to one corresponding GBTX and then two fiber cables are used to transmit the data from the two GBTX chips to the MM trigger processor. An overview of the trigger path is shown in figure 10.
The test objective of the trigger path validation is the confirmation of the electrical and optical connectivity by sending test pulses to all VMMs of a double wedge and reading out the ART data from the TP. An ART test run of a double-wedge where all VMM channels are pulsed sequentially and produce a map of the ARTs that are readout out on the TP (10 pulses sent to 3 different channels on each VMM) is shown in figure 11. Ideally each bin content would be 30. No bins with 0 content lead to sign-off on electrical and optical connectivity of the chamber. A few low efficiency spots that can be seen in figure 11 are attributed to dead VMM channels that had not been masked out.

Conclusions
The New Small Wheel is a fully redundant trigger and tracking detector system, adequately supported by an advanced electronics scheme and ready to handle the challenges of increased instantaneous luminosity at the HL-LHC. The NSW precision tracking and trigger detectors are able to work at high rates and will provide trigger and tracking primitives fully compliant with the HL-LHC rates. The electronics is designed to provide sufficient bandwidth even at a readout rate of 1 MHz for data acquisition and trigger paths, as well as low latency for the latter. The electronics performance of the Micromegas sector has been studied during sector integration and commissioning at CERN and tests prove that the design goals are achievable.