Upgrade of the ATLAS Level-0 TGC Endcap Muon Trigger for HL-LHC

The Level-0 endcap muon trigger system for the ATLAS experiment at the HL-LHC, which performs a fast muon reconstruction using the Thin Gap Chamber (TGC), is being developed to cope with more than three times higher luminosity environment and achieve a better performance. The efficiency in the high-p T region was found to be 9% higher than the current system. The TGC hit signals digitized at the frontend electronics are sent to the backend, and muon candidates are reconstructed using the hits. Then, the candidates are combined with information from other detectors to refine transverse momentum (p T) reconstruction and reduce fake trigger candidates. The precise online estimation of p T allows us to apply highly efficient trigger condition to select events that contains muons with high p T. The Sector Logic (SL) is responsible for the online fast reconstruction in the L0 Muon Trigger system, and the algorithms are implemented in a large-scale modern FPGA on the SL. Each step of the reconstruction algorithms is first implemented as individual modules, and all trigger algorithms run sequentially as a chain in a combined firmware. The trigger algorithms are being tested on the prototype trigger board, the SL. The resource usage of the FPGA is reasonable and the trigger latency is within the acceptable limit.


Introduction
The ATLAS experiment aims to study the particle physics Standard Model precisely and search for physics beyond the Standard Model by using the ATLAS [1] detector at the Large Hadron Collider (LHC) [2], the world's highest energy accelerator.High Luminosity LHC (HL-LHC) project will start in 2029 to obtain a total integrated luminosity of 3000 fb −1 .HL-LHC provides collisions with the center-of-mass energy of √  = 14 TeV and the peak instantaneous luminosity of 7.5 × 10 34 cm −2 s −1 , which is more than three times higher than the current Run-3.
The ATLAS trigger system will be upgraded for HL-LHC, called "Phase-II upgrade" [3].The upgraded trigger system consists of the first-level hardware-based trigger, the Level-0 (L0) trigger, and the following software-based Event Filter.The L0 trigger latency and the maximum allowed trigger rate in the Phase-II system are 10 μs and 1 MHz, respectively, which are significantly extended from those specifications of the current first-level trigger system of 2.5 μs and 100 kHz.The Event Filter will narrow the event rate down to 10 kHz.

The first-level endcap muon trigger and its Phase-II upgrade
The level-0 TGC endcap muon trigger system reconstructs muons in the in the endcap (|| > 1.05, where  is the pseudo-rapidity) region.Thin Gap Chamber [4] (TGC) is a multi-wire proportional chamber muon detector with fast response.The TGC system consists of one triplet gas-gap module and two doublet gas-gap modules in the endcap region, which is called TGC Big Wheel (BW).The TGC BW has seven layers in total.Each layer has orthogonal readout channels; anode wires for  coordinate and cathode strip for  coordinate.
Trigger electronics for the Endcap Muon Trigger will be fully upgraded in the Phase-II upgrade for triggering events with enough sensitivity in the high-luminosity environment, exploiting modern high speed serial link and large-scale FPGA.The L0 Endcap Muon Trigger first reconstructs muon candidates using TGC hits (L0TGC).The schematic diagram of the L0TGC is shown in figure 1 (left).The frontend electronics of the system sends all the hits to the backend trigger processor board (Endcap Sector-Logic, SL), which hosts a large-scale FPGA, Xilinx Virtex Ultrascale+ XCVU13P [5] (see figure 1), and executes all of the reconstruction algorithms.The data rate that a Endcap SL recieves from TGC BW via PS -1 -  boards reaches 464 Gbps.A Mercury XU5 MPSoC mezzanine card is mounted on the SL board for configuration and communication, and the FireFly modules are used for optical communication with other boards.After L0TGC, tracks are refined using precise information of MDT [4], which is called L0MDT.The current trigger system was designed in the late 90s and as a consequence, the performance of the trigger system is limited in terms of the resolution, minimum number of hits, and number of candidates.Through the upgrade, for example, the position resolution after reconstruction with hits of TGC BW will be 32 times better than the current.

L0 TGC endcap muon trigger logic and its implementation on the firmware
The objectives of the L0 TGC trigger algorithm are to reconstruct muon candidates basically as straight lines and estimate their transverse momentum ( T ) by the angles of the lines.A trigger logic has been developed within the resources of the FPGA and the latency budget, which is 2.15 μs from the bunch crossing until sending the segments to L0MDT.The logic is a sequence of the following logic blocks.

Wire/Strip Segment Reconstruction
In the first step of the logic, the straight track is reconstructed in -coordinate and -coordinate separately using the wire and the strip readout of TGC BW.They are called the Wire and Strip Segment Reconstruction.The SL takes a local coincidence in the triplet and doublet modules of the TGC BW first, and then connects the three stations to reconstruct straight tracks in  and -coordinate independently.
The reconstruction provides incident angles and positions on the outermost pivot layer as a proxy for momentum measurement.Look Up Table (LUT) approach allows us to reconstruct the segment with a short and fixed latency for angle reconstruction instead of fitting.To achieve high resolution, an -2 -UltraRAM (URAM), a 288kb large memory block with a fixed width of input address (12 bits) and output data (72 bits) is used.The angles of the combinations of some grouped channels are readout using a fixed 72-bit word to select the most probable track from clustered hits.

Wire-Strip Coincidence
Straight track segments reconstructed separately in  and  with wire and strip readout are combined at "Wire-Strip Coincidence" block.- pairs of the reconstructed incidence angles and pivot position can be mapped for  T estimation, which can be expressed as a 2D window (Coincidence Window, CW).The granularity of the bins of the CW is not equal to maximize the resolution within the limited resources.A CW is implemented on a 36kb BlockRAM (BRAM).

Inner Coincidence
Finally, coincidence between track candidates in TGC BW and inputs from other detectors is taken to suppress fake trigger candidates, charged particles not originated from the interactions point.The other advantage is to improve the momentum resolution.This step is called "Inner Coincidence".The  T is refined by the Inner Coincidence, which is implemented in LUTs.In the region of 1.05 < || < 1.3, information from TGC on the Endcap Inner station (TGC EI), Resistive Plate Chambers overlapping with TGC BW coverage on the Barrel Inner station (RPC BIS78 [6]), and supplementary the most outer layers of Tile Calorimeter [7] cells are used for coincidence.In the region of 1.3 < || < 2.4, Micro Megas and small-strip TGC on the New Small Wheel [8] (NSW) are used.Since each coincidence logic uses a large but different amount of resources, it is implemented using various RAMs (UltraRAM, BlockRAM, Distributed LUT) for optimizing resource utilization.After the Inner Coincidence block is completed, selected tracks are sent to L0MDT.

Estimated efficiency
The estimated trigger efficiency of the L0TGC is shown in figure 2. The developed trigger logic is emulated on the software.We prepared a full-chain of firmware covering a limited eta-phi space for testing purposes and a test bench for running behavioural simulation with those from the fully-software-based simulator.Consistent outputs between them are obtained for most cases for the injected test patterns.Consistent results between hardware and software in terms of the  T are obtained for most of the cases, more than 99%.The four levels of thresholds of the  T are applied.A 94% efficiency is obtained in the plateau region for each threshold, and on the other hand, muons with lower- T than the thresholds are rejected efficiently.The efficiency in the plateau region is higher by 9% compared to the current system.

Integration of the trigger firmware blocks on the SL 1st prototype
We have integrated the trigger logic sequence to make a full chain trigger firmware for the whole region that one large-scale FPGA on the SL covers.A block diagram of the full-chain firmware is shown in figure 3. The coverage of each trigger module is different and careful treatment is necessary to connect between different modules.The whole logic including trigger, readout, and some control logic was integrated and tested with the SL prototype.SL FPGA consists of 4 silicon dies called Super Logic Regions (SLRs).Associated with I/O assignment optimization, we designed the following SLR usage; BW Segment Reconstruction is separately implemented on 3 SLRs and integrated at SLR1 for Inner Coincidence, as shown in figure 4. Information after segment reconstruction with TGC BW is -3 -  sent via Super Long Lines (SLL).We implemented proper numbers of pipeline registers, reduced the number of bits to send to SLR1 to satisfy the timing constraint around SLL connectivity.Table 1 shows the resource utilization in each SLR, which shows a moderate value.The latency of the trigger logic is 0.49 μs, which is also within the requirement (1.1 μs).

JINST 19 C03010
The test of the trigger logic in the whole region is progressing using the first prototype.The outputs are compared between software simulations, firmware simulations, and newly developed bit-wise software simulations which emulates the firmware trigger logic completely.After the verification of hardware properties, the SL second prototype is being produced with some minor hardware improvements.

Conclusion
The Level-0 TGC Endcap Muon Trigger for HL-LHC has been developed.All hits from TGC BW are sent to SL, and muon reconstruction including making coincidence with other detectors is processed at the large-scale FPGA in the SL.Trigger logic was implemented, expanded, and connected on the firmware, and the estimated efficiency shows high plateau efficiency for high- T muons.The chain of the logic was optimized and successfully integrated into the SL first prototype with moderate resource utilization and latency.

Figure 1 .
Figure 1.Left: schematic of the L0TGC electronics.All of the TGC BW hit information are digitized at ASDs, determined which bunch-crossing they are from, and sent to Endcap Sector Logic for reconstruction.JAT-Hub is a independent control and recovery module for PS boards.Endcap Sector Logic communicates with various modules, including other trigger processors (NSW, TILE, BIS78, MDT Trigger Processor and MUCTPI), control systems (TDAQ server, DCS and ATCA Self Manager), and FELIX for readout.Right: photo of the Endcap SL first prototype.

Figure 2 .Figure 3 .Figure 4 .
Figure 2. L0TGC efficiency at the endcap region (1.05 < || < 2.4) for  T thresholds at 5, 10, 15, 20 GeV (pink, green, blue, red), evaluated with a single muon Monte Carlo simulation without pileup collisions accounted.The trigger efficiency is estimated with respect to offline muons, where the offline muons satisfy the standard offline 'Medium' quality requirement, and is shown as a function the offline  T .Smeared truth positions on the Monitored Drift Tube and the Cathode Strip Chamber in the Endcap inner stations in the Run-2 geometry are used to emulate the inputs from the NSW and the TGC EI.Truth particle information is extrapolated and smeared to emulate the inputs from the RPC BIS78.

Table 1 .
Resource utilization in the SL first prototype.Configurable Logic Block (CLB), a basic repeating logic resource consists of small LUTs and Flip-Flops (FF).