Due to a planned intervention, some web lectures may be unavailable on Wednesday, June 26th from 12:00 to 14:00 CEST.

CERN Accelerating science

CERN-wide meetings, trainings and events

Последно добавени:
2024-06-21
08:57
HDL on git (Hog) / Aranzabal Barrio, Nordin (speaker)
The coordination of firmware development among numerous developers is a major issue in any collaboration. This requires standardised tools for ensuring binary file traceability and firmware synthesis with Place and Route repeatability. To address these problems, we present Hog, a free and open-source tool for maintaining HDL on git. Hog integrates within HDL IDEs (Intel Quartus, MicroSemi Libero, AMD Vivado and ISE) on both Windows and Linux platforms, minimizing overhead labour, and easing the use of advanced git features. Hog is a set of Tcl/Shell scripts with an appropriate workflow for managing HDL designs in a git repository. Hog is included as a submodule, a simple method of maintaining HDL code on git requiring no further installation. This method allows for automatic detection of any change in the source code, embedding the git tag and commits SHA in the bitstream. Hog exploits the use of the git CI to automatically compile and simulate the project generating tags and releases..
2024 - 0:41:35. FPGA Developers' Forum (FDF); 1st FPGA Developers' Forum (FDF) meeting External links: Talk details; Event details In : 1st FPGA Developers' Forum (FDF) meeting

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2024-06-19
14:44
Probing new signatures for semi-visible jets at the LHC / Cazzaniga, Cesare Tiziano (speaker) (ETH Zurich (CH))
The Hidden Valley scenario consists of a set of models where the Standard Model is accompanied by a Hidden Sector and connected with it via a heavy mediator or a weak coupling. If realised in nature, the Hidden Valley scenario may result in unusual and little-studied phenomena at the LHC. [...]
2024 - 0:21:55. Workshops; Roadmap of Dark Matter models for Run 3 External links: Talk details; Event details In : Roadmap of Dark Matter models for Run 3

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2024-06-19
14:44
Foundation Models as a new tool to uncover the dark sector? / Birk, Joschka (speaker) (Hamburg University (DE))
2024 - 0:17:15. Workshops; Roadmap of Dark Matter models for Run 3 External links: Talk details; Event details In : Roadmap of Dark Matter models for Run 3

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2024-06-19
14:44
SIFTing for dark shower signals / Shepherd, William (speaker)
I present ongoing work seeking to identify the presence of dark shower phenomena in otherwise ordinary-seeming jets using jet substructure techniques with a particular focus on the recently-proposed SIFT algorithm. The aim is to explicitly identify the mass scale signature of the dark shower products which then promptly decay back into SM quarks, giving effectively normal-looking SM jets. [...]
2024 - 0:24:15. Workshops; Roadmap of Dark Matter models for Run 3 External links: Talk details; Event details In : Roadmap of Dark Matter models for Run 3

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2024-06-19
14:44
Discussion and wrap up / Sinha, Sukanya (speaker) (University of Manchester (GB)) ; Kulkarni, Suchita (speaker) (University of Graz) ; De Cosa, Annapaola (speaker) (ETH Zurich (CH))
2024 - 0:26:05. Workshops; Roadmap of Dark Matter models for Run 3 External links: Talk details; Event details In : Roadmap of Dark Matter models for Run 3

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2024-06-19
14:35
Open source formal verification with SymbiYosis / Thoma, Yann (speaker) (HEIG-VD)
Verification of digital systems is an art, and often implemented through testbenches and functional verification. Formal verification is an alternative approach where we describe properties representing the expected behaviour of the system. It allows to prove these properties are fulfilled through assertions. [...]
2024 - 0:32:18. FPGA Developers' Forum (FDF); 1st FPGA Developers' Forum (FDF) meeting External links: Talk details; Event details In : 1st FPGA Developers' Forum (FDF) meeting

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2024-06-19
14:34
Assertion-Based Formal Debugging During RTL Development / Engelhardt, N. (speaker) (YosysHQ)
Traditionally, assertion-based formal verification is performed after RTL development is complete, by a separate team of verification engineers, to comprehensively prove conformance of a design. While this provides the highest safety guarantees, it is also a lengthy endeavour. [...]
2024 - 0:32:58. FPGA Developers' Forum (FDF); 1st FPGA Developers' Forum (FDF) meeting External links: Talk details; Event details In : 1st FPGA Developers' Forum (FDF) meeting

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2024-06-19
14:34
Automatic code generation for managing the firmware and software for configuration/status registers and memories in the ATLAS Level-1 Central Trigger / Kulinska, Anna Malgorzata (speaker) (CERN)
Large FPGA firmware designs, such as the ones used in the trigger systems of HEP experiments, typically contain many hundreds of configuration/status registers and memories. Managing the required HDL code and software for these can become challenging. [...]
2024 - 0:27:38. FPGA Developers' Forum (FDF); 1st FPGA Developers' Forum (FDF) meeting External links: Talk details; Event details In : 1st FPGA Developers' Forum (FDF) meeting

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2024-06-19
14:34
YML2HDL tool / Costa De Paiva, Thiago (speaker) (University of Massachusetts (US))
As the technology advances, FPGA devices become more powerful and enable more complex projects. As a result, developers with diverse backgrounds, including different hardware description languages, are required to work together. [...]
2024 - 0:17:54. FPGA Developers' Forum (FDF); 1st FPGA Developers' Forum (FDF) meeting External links: Talk details; Event details In : 1st FPGA Developers' Forum (FDF) meeting

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2024-06-19
14:34
Closing Remarks / Gonnella, Francesco (speaker) (University of Birmingham (GB))
2024 - 0:10:19. FPGA Developers' Forum (FDF); 1st FPGA Developers' Forum (FDF) meeting External links: Talk details; Event details In : 1st FPGA Developers' Forum (FDF) meeting

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