2025-05-23
10:38 |
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Architecting FPGA for low power Leadership
/ Shah, Hardik (speaker) (Lattice Semiconductor)
Reducing power consumption in FPGAs offers a range of benefits across various applications, including: extended battery life, simplified heat sink requirements, reduced complexity of the PCB power network, the potential for smaller package sizes, minimized heat-related measurement errors, and increased component longevity. Achieving energy-efficient FPGA design demands a comprehensive approach—from product strategy to the choice of process technology and on-chip architecture. [...]
2025 - 1555.
FPGA Developers' Forum (FDF); 2nd FPGA Developers' Forum (FDF) meeting
External links: Talk details; Event details
In : 2nd FPGA Developers' Forum (FDF) meeting
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Notice détaillée
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2025-05-23
10:38 |
Notice détaillée
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2025-05-23
08:25 |
Notice détaillée
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2025-05-23
08:25 |
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Low Jitter Frame Clock Recovery in Xilinx Ultrascale+ Transceivers
/ Bachek, Paul (speaker) (Brookhaven National Lab)
The Electron Ion Collider (EIC) Timing Data Link requires high precision clock recovery for accelerator master clock distribution. To meet the performance requirements a novel method for extracting a low jitter data frame clock from serial encoded data using Xilinx Ultrascale+ transceivers is presented. [...]
2025 - 1462.
FPGA Developers' Forum (FDF); 2nd FPGA Developers' Forum (FDF) meeting
External links: Talk details; Event details
In : 2nd FPGA Developers' Forum (FDF) meeting
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Notice détaillée
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2025-05-23
08:25 |
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Disruptive Efinix Quantum Architecture
/ Werner, Harald (speaker) (Efinix Inc.)
In this session we will explain the new disruptive architecture from our new low power, high speed FPGA Families. This architecture is different to the standard FPGA architecture and has a lot of benefits compare to the old architecture [...]
2025 - 1705.
FPGA Developers' Forum (FDF); 2nd FPGA Developers' Forum (FDF) meeting
External links: Talk details; Event details
In : 2nd FPGA Developers' Forum (FDF) meeting
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Notice détaillée
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2025-05-23
08:25 |
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Abstract interface modelling for better genericity and code clarity
/ Pouillon, Nicolas (speaker) (Ellisys)
AXI4 (Memory-Mapped, Stream) is a well established set of flexible bus interfaces. They can support various address and/or data widths, have optional support for bursts, byte strobing, back-pressure, sideband signals, etc.
Writing generic yet easily maintainable AXI-compatible modules is hard: implementation must take care of abiding interoperability rules for optional signals at all times. [...]
2025 - 1875.
FPGA Developers' Forum (FDF); 2nd FPGA Developers' Forum (FDF) meeting
External links: Talk details; Event details
In : 2nd FPGA Developers' Forum (FDF) meeting
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Notice détaillée
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2025-05-23
08:24 |
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FPGA Implementation of Next-Generation Reservoir Computing for predicting dynamical systems
/ Folhadela, João (speaker) (Deutsches Zentrum für Luft- und Raumfahrt e.V. (DLR))
Reservoir Computing (RC) is a new paradigm in Machine Learning, alternative to Neural Networks on predicting dynamical systems, offering advantages in efficiency and computational simplicity. These characteristics make RC particularly well-suited for implementation on resource-constrained hardware such as FPGAs, enabling low-power, real-time edge computing. [...]
2025 - 916.
FPGA Developers' Forum (FDF); 2nd FPGA Developers' Forum (FDF) meeting
External links: Talk details; Event details
In : 2nd FPGA Developers' Forum (FDF) meeting
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Notice détaillée
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2025-05-23
08:24 |
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Accelerating Transformer Neural Networks on FPGAs for High Energy Physics Experiments
/ Wojcicki, Filip (speaker) (Imperial College London)
The ever-increasing data rates and ultra-low-latency requirements of particle physics experiments demand innovations for real-time decision-making. Transformer Neural Networks (TNNs) have demonstrated state-of-the-art performance in classification tasks, including jet tagging, but implementations on CPUs and GPUs fail to meet the constraints for real-time triggers. [...]
2025 - 1384.
FPGA Developers' Forum (FDF); 2nd FPGA Developers' Forum (FDF) meeting
External links: Talk details; Event details
In : 2nd FPGA Developers' Forum (FDF) meeting
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Notice détaillée
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2025-05-22
17:07 |
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HDLRegression: A reliable and efficient tool for FPGA regression testing
/ Elvegård, Marius (speaker) (Inventas)
HDLRegression was developed to provide a reliable, efficient tool for regression testing of maintenance testbenches for UVVM and other FPGA project testbenches. It simplifies simulations with minimal changes—just a single comment in the testbench entity—making it easy to integrate into existing projects.
One big advantage is its independence from any specific verification framework, enabling use with UVVM, OSVVM, VUnit, or any other in-house tools for maximum flexibility.
As FPGA designs grow more complex, numerous tests are needed to verify functionality. [...]
2025 - 1808.
FPGA Developers' Forum (FDF); 2nd FPGA Developers' Forum (FDF) meeting
External links: Talk details; Event details
In : 2nd FPGA Developers' Forum (FDF) meeting
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Notice détaillée
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2025-05-22
16:23 |
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Generating memory maps with Cheby and Reksio
/ Gingold, Tristan (speaker) (CERN) ; Bielawski, Bartosz (speaker) (CERN)
Cheby is an HDL tool which transforms a YAML description of a memory map into HDL code, C header, python constants or HTML documentation. The tool was designed to be flexible: it supports many buses, many kinds of peripherals (registers, memories, wires, submodules) as well as structural features like repetition. [...]
2025 - 1484.
FPGA Developers' Forum (FDF); 2nd FPGA Developers' Forum (FDF) meeting
External links: Talk details; Event details
In : 2nd FPGA Developers' Forum (FDF) meeting
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Notice détaillée
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