CERN Accelerating science

Article
Title	The ALICE silicon pixel detector readout electronics
Author(s)	Krivda, M (Kosice, IEF) ; Ban, J (Kosice, IEF) ; Burns, M (CERN) ; Caselle, M (INFN, Bari) ; Kluge, A (CERN) ; Manzari, V (INFN, Bari) ; Torcato de Matos, C (CERN) ; Morel, M (CERN) ; Riedler, P (CERN) ; Aglieri Rinella, G (CERN) ; Sandor, L (Kosice, IEF) ; Stefanini, G (CERN)
Publication	2010
Number of pages	3
In:	Nucl. Instrum. Methods Phys. Res., A 617 (2010) 549-551
In:	11th Pisa Meeting on Advanced Detectors on Frontier Detectors For Frontier Physics, La Biodola, Italy, 24 - 30 May 2009, pp.549-551
DOI	10.1016/j.nima.2009.10.047
Subject category	Detectors and Experimental Techniques
Accelerator/Facility, Experiment	CERN LHC ; ALICE
Abstract	The ALICE silicon pixel detector (SPD) constitutes the two innermost layers of the ALICE inner tracking system (ALICE Collaboration, 1999) [1]. The SPD is built with 120 detector modules (half-staves) and contains about 10 million pixels in total. The half-staves are connected to the off-detector electronics, housed in a control room 100 m away, via bidirectional optical links. The stream of data from the front-end electronics is processed in 20 VME readout modules, called routers, based on FPGAs. Three 2-channel link-receiver daughter cards, also based on FPGAs, are plugged in each router. Each link-receiver card receives data via the optical link from two half-staves, applies the zero suppression and passes them to the router to be processed and sent to the ALICE–DAQ system through the detector data link (DDL). The SPD control, configuration and data monitoring are performed using the VME interface embedded in the router.

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