<?xml version="1.0" encoding="UTF-8"?>
<articles>
<article xmlns:xlink="http://www.w3.org/1999/xlink/">
  <front>
    <article-meta>
      <title-group>
        <article-title>The Upgrade of the PreProcessor System of the ATLAS Level-1 Calorimeter Trigger</article-title>
      </title-group>
      <contrib-group>
        <contrib contrib-type="author">
          <name>
            <surname>Andrei</surname>
            <given-names>V</given-names>
          </name>
        </contrib>
      </contrib-group>
      <pub-date pub-type="pub">
        <year>2012</year>
      </pub-date>
      <self-uri xlink:href="http://cds.cern.ch/record/1477973"/>
      <self-uri xlink:href="http://cds.cern.ch/record/1475242"/>
      <self-uri xlink:href="http://cds.cern.ch/record/1477973/files/ATL-DAQ-SLIDE-2012-520.pdf"/>
    </article-meta>
    <abstract>The ATLAS Level-1 Calorimeter Trigger is a pipelined system to identify high-pT objects and to build energy sums within a fixed latency of ~2 us. It consists of a PreProcessor, which conditions and digitises analogue calorimeter signals, and two object-finding processors. The PreProcessor's tasks are implemented on a Multi-Chip Module, holding ADCs, time-adjustment and digital processing ASICs, and LVDS serialisers. A pin-compatible substitute, based on today's technology, like dual-channel ADCs and FPGAs, has been built to improve the BCID and pedestal subtraction algorithms. Test results with the first prototype are presented.</abstract>
  </front>
  <article-type>PUBLATLASSLIDE</article-type>
</article>

</articles>