1478361 20130205140029.0 oai:cds.cern.ch:1478361 cerncds:FULLTEXT ATL-DAQ-SLIDE-2012-529 eng ATL-COM-DAQ-2012-164 "Wenzel, V Johannes Gutenberg Universitaet Mainz" The ATLAS collaboration "Bauss, B Johannes Gutenberg Universitaet Mainz" "Buescher, V Johannes Gutenberg Universitaet Mainz" "Degele, R Johannes Gutenberg Universitaet Mainz" "Ji, W Johannes Gutenberg Universitaet Mainz" "Moritz, S Johannes Gutenberg Universitaet Mainz" "Reiss, A Johannes Gutenberg Universitaet Mainz" "Schaefer, U Johannes Gutenberg Universitaet Mainz" "Simioni, E Johannes Gutenberg Universitaet Mainz" "Tapprogge, S Johannes Gutenberg Universitaet Mainz" An FPGA based Topological Processor Prototype for the ATLAS Level-1 Trigger Upgrade 2012 CERN Geneva 17 Sep 2012 1 p SLIDES By 2014 the LHC will collide proton bunches at 14 TeV with an increased instantaneous luminosity up to 3×10^34cm−2s−1. A reduction on the trigger rate can be achieved by applying topological cuts adopting a new FPGA based module in the L1 trigger: the Topological Processor (TP). This presentation focuses on the design of the first TP prototype and on the test results on algorithm implemented in the TP demonstrator in order to measure latency and FPGA logic utilization. SLIDE CERN CDS-Invenio WebSubmit Detectors and Experimental Techniques SzGeCERN DAQ and Trigger SzGeCERN CERN Trigger CERN topology CERN topological algorithm CERN topological CERN FPGA CERN TDAQ CERN upgrade CERN xilinx CERN l1calo CERN atlas CERN algorithms CERN bandwidth CERN calorimeter CERN concentrator CERN demonstrators CERN latency CERN INTNOTE PRIVATLAS PUBLATLASSLIDE CERN LHC ATLAS PH-EP http://cds.cern.ch/record/1476713 Original Communication (restricted to ATLAS) http://cds.cern.ch/record/1478361/files/ATL-DAQ-SLIDE-2012-529.pdf eduard.simioni@cern.ch wenzelv@students.uni-mainz.de volker.wenzel@cern.ch n 201270 91 1459551 oxford20120917 PUBLIC 000726086CER PUBLATLASSLIDE