<?xml version="1.0" encoding="UTF-8"?>
<articles>
<article xmlns:xlink="http://www.w3.org/1999/xlink/">
  <front>
    <article-meta>
      <title-group>
        <article-title>ATLAS Level-1 Calorimeter Trigger Upgrade for Phase-I</article-title>
      </title-group>
      <contrib-group>
        <contrib contrib-type="author">
          <name>
            <surname>Qian</surname>
            <given-names>W</given-names>
          </name>
          <aff>
            <institution>Rutherford</institution>
          </aff>
        </contrib>
      </contrib-group>
      <pub-date pub-type="pub">
        <year>2012</year>
      </pub-date>
      <self-uri xlink:href="http://cds.cern.ch/record/1489947"/>
      <self-uri xlink:href="http://cds.cern.ch/record/1484884"/>
      <self-uri xlink:href="http://cds.cern.ch/record/1489947/files/ATL-DAQ-PROC-2012-052.pdf"/>
    </article-meta>
    <abstract>The ATLAS Level-1 Trigger requires several upgrades to maintain physics sensitivity as the LHC luminosity is raised. One of the most challenging is the electron trigger, with a major development planned for installation in 2018. New on-detector electronics will be installed to digitize electromagnetic calorimetry signals, providing trigger access to shower profile information. The trigger processing will be ATCA-based, with each multi-FPGA module processing ~1 Tbit/s of calorimeter digits within the current 2.5 microseconds Level-1 Trigger latency limit. This paper will address the system architecture and design, and give the status of a current technology demonstrator.</abstract>
  </front>
  <article-type>INTNOTEATLASPUBL</article-type>
</article>

</articles>