CERN Accelerating science

ATLAS Note
Report number	ATL-INDET-PROC-2012-026
Title	Implementation and Tests of FPGA-embedded PowerPC in the control system of the ATLAS IBL ROD card
Author(s)	Balbi, G (INFN, Bologna) ; Bindi, M (INFN, Bologna) ; Falchieri, D (INFN, Bologna ; Bologna U.) ; Gabrielli, A (INFN, Bologna ; Bologna U.) ; Furini, M (INFN, Bologna) ; Kugel, A (Heidelberg U.) ; Travaglini, R (INFN, Bologna) ; Wensing, M (Wuppertal U.)
Corporate Author(s)	The ATLAS collaboration
Publication	2012
Imprint	12 Nov 2012
Number of pages	8
In:	Topical Workshop on Electronics for Particle Physics, Oxford, UK, 17 - 21 Sep 2012
Subject category	Detectors and Experimental Techniques
Accelerator/Facility, Experiment	CERN LHC ; ATLAS
Free keywords	Data acquisition circuits ; Detector control systems ; Digital electronic circuits
Abstract	The Insertable B-layer project is planned for the upgrade of the ATLAS experiment at LHC. A silicon layer will be inserted into the existing Pixel Detector together with new electronics. The readout off-detector system is implemented with a Back-Of-Crate module implementing I/O functionality and a Readout-Driver card (ROD) for data processing. The ROD hosts the electronics devoted to control operations implemented both with a back- compatible solution (via DSP) and with a PowerPC embedded into an FPGA. In this document major firmware and software achievements concerning the PowerPC implementation, tested on ROD prototypes, will be reported.
Copyright/License	Preprint: (License: CC-BY-4.0)