1629557 20170524112829.0 ARTICLE CERN WEBOFSCIENCE-NEW-201311 1459551 C12014 oxford20120917 ARTICLE ConferencePaper Moreira, P CERN Tavernier, F CERN C12014 JINST 7 2012 http://cds.cern.ch/record/1629557/files/jinst_7_12_C12014.pdf IOP Open Access article A radiation-hard PLL for frequency multiplication with programmable input clock and phase-selectable output signals in 130 nm CMOS DOI 10.1088/1748-0221/7/12/C12014 oai:cds.cern.ch:1629557 cerncds:FULLTEXT cerncds:CERN:FULLTEXT cerncds:CERN 2012 A PLL (ePLL) is presented that is intended to be used as a frequency multiplier. The ePLL accepts 40, 80, 160 or 320 MHz as a reference and generates clocks at the same frequencies, regardless of the input clock. Moreover, the outputs are available with a phase resolution of 90 degrees for the 40, 80 and 160 MHz output and 22.5 degrees for the 320 MHz output. The radiation-hard design, integrated in a 130 nm CMOS technology, is able to operate at a supply voltage between 1.2V and 1.5V. CC-BY-3.0 Publication Topical Workshop on Electronics for Particle Physics, Oxford, ENGLAND, SEP 17-21, 2012 13 Poltorak, K CERN n 201347 a2012 eng SzGeCERN Detectors and Experimental Techniques