Poltorak, K Moreira, P Tavernier, F A radiation-hard PLL for frequency multiplication with programmable input clock and phase-selectable output signals in 130 nm CMOS JINST C12014 7 A PLL (ePLL) is presented that is intended to be used as a frequency multiplier. The ePLL accepts 40, 80, 160 or 320 MHz as a reference and generates clocks at the same frequencies, regardless of the input clock. Moreover, the outputs are available with a phase resolution of 90 degrees for the 40, 80 and 160 MHz output and 22.5 degrees for the 320 MHz output. The radiation-hard design, integrated in a 130 nm CMOS technology, is able to operate at a supply voltage between 1.2V and 1.5V. eng 2012

http://cds.cern.ch/record/1629557/files/jinst_7_12_C12014.pdf;

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