Marconi, Sara Hemperek, Tomasz Placidi, Pisana Scorzoni, Andrea Conti, Elia Christiansen, Jorgen 10.1109/PRIME.2017.7974142 201-204 Clocks Optimization Latches Integrated circuits Power demand Switching circuits Degradation image sensors low-power electronics readout electronics low-power optimisation pixel array architecture next generation high-energy physics detectors large-scale pixel readout chip RD53 collaboration high-luminosity upgrades ATLAS CMS experiment CERN advanced digital design tool simulation tool architectural choice implementation choice pixel chip design pixel chip optimisation serial powering scheme low-power design technique size 65 nm 2017 2017 A large scale pixel readout chip is being designed by the RD53 Collaboration, in order to prove the suitability of 65 nm technology for the extreme operating conditions foreseen for the High Luminosity upgrades of the ATLAS and CMS experiments at CERN. The use of advanced digital design and simulation tools is essential to guide architectural and implementation choices for the design and optimisation of pixel chips which will be powered from a serial powering scheme. In this work, low power design techniques are reviewed and critically selected based on the requirements of the target application. Chosen techniques are adopted and results of the low power optimisation are presented for a basic unit of the system.