 | High-level logic diagram of the HCCStar, showing the flow of control signals from the ``stave side" to the ABCStars on the ``hybrid side", which then produce data packets. The packet builder (purple) is responsible for merging the ABCStar input streams into single output packets for every event, and is one of the most complex parts of the chip. |
 | Architecture of a standard cocotb testbench. The design under test (DUT) is cosimulated using a standard Verilog or VHDL simulator (the HCCStar verification was done using the Cadence Incisive simulator) and controlled via Python. |
 | Diagram of an ITk Strips module from one of the inner barrel layers. Both front-end readout chips sit on an electrical hybrid (green) above the silicon sensors (blue). Depending on the exact geometry, modules can have one or two hybrids. |
 | : Total time to process R3 triggers |
 | : Total time to process L1 triggers |