<?xml version="1.0" encoding="UTF-8"?>
<references>
<reference>
  <a1>Schwemmer, Rainer</a1>
  <a2>Neufeld, Niko</a2>
  <t1>A 32 Terabit/s Data Acquisition from Mostly COTS Components</t1>
  <t2>IEEE Trans. Nucl. Sci.</t2>
  <sn/>
  <op>1747-1751</op>
  <vo>62</vo>
  <ab>The Large Hadron Collider beauty (LHCb) data acquisition after 2019 will need to perform event-building at an aggregated band-width of 32 Tbit/s. Apart from the technological challenges described in various papers also at this conference, the key challenge is to come up with an architecture which minimises the cost, while providing a system which can be maintained by a small team for a long time and which scales well. In this paper we present the analyses we have been doing to minimise the cost, the R&amp;D; topics we derived from that and how we combined all this into a coherent proposal which allows us to come up with a system which not only today fits the budgetary constraints of LHCb, but also will allow profiting from any main-stream technological development. We achieve this by aligning our system needs as much as possible to data-centre mass-market commercial of the shelf (COTS) products; by minimising the number of optical interconnects and by optimising the physical layout of the system. This system requires only one piece of custom-made hardware, and even this could, for a smaller setup be replaced by a commercially available item. We believe that the reasoning behind this design can be beneficial to any large, high-rate data acquisition system.</ab>
  <la>eng</la>
  <k1>data acquisition;
                high energy physics instrumentation computing;
                linear accelerators;
                optical interconnections;
                COTS components;
                Large Hadron Collider beauty data acquisition;
                high-rate data acquisition system;
                optical interconnects;
                Bandwidth;
                Buildings;
                Data acquisition;
                Detectors;
                Field programmable gate arrays;
                Hardware;
                Servers;
                multiprocessor interconnection networks;
                network topology;
                next generation networking;
                real-time systems;;
                </k1>
  <pb>IEEE</pb>
  <pp/>
  <yr>2015</yr>
  <ed/>
  <ul>http://cds.cern.ch/record/2710799/files/07153573.pdf;
	http://cds.cern.ch/record/2710799/files/07153573.gif?subformat=icon;
	http://cds.cern.ch/record/2710799/files/07153573.jpg?subformat=icon-180;
	http://cds.cern.ch/record/2710799/files/07153573.jpg?subformat=icon-700;
	</ul>
  <no>Imported from Invenio.</no>
</reference>

</references>