Aspell, P
Barney, D
Beaumont, Y
Borkar, S
Borkar, A P
Domeniconi, J
Futyan, D I
Go, A
Lalwani, S
Palomares, C
Prunier, R
Reynaud, S
A flexible stand-alone testbench for characterizing the front-end electronics for the CMS preshower detector under LHC-like timing conditions
http://documents.cern.ch/cgi-bin/setlink?base=yellowarticle&categ=2002-003&id=p209;
http://cds.cern.ch/record/593923/files/p209.pdf;
Imported from Invenio.
Aspell, P
Barney, D
Elliot-Peisert, A
Bloch, P
Go, A
Kloukinas, Kostas C
Löfstedt, B
Palomares, C
Reynaud, S
Tzoulis, N
DeltaStream: A 36 channel low noise, large dynamic range silicon detector readout ASIC optimised for large detector capacitance
http://documents.cern.ch/cgi-bin/setlink?base=yellowarticle&categ=2001-005&id=p295;
http://cds.cern.ch/record/530649/files/p295.pdf;
Imported from Invenio.
Aspell, P
Conception et mise au point de l'électronique frontale du détecteur de pied de gerbe (Preshower) de l'expérience CMS
Modern particle physics collider experiments consist of a number of macroscopic modules each consisting of large number of sensors measuring charge deposition from traversing particles. The CMS Preshower detector is designed as a sampling calorimeter producing electromagnetic showers for incident electrons and photons resulting from LHC p-p interactions. The ultimate aim is to provide neutral pion / gamma separation reducing the background to the most promising Higgs channel, SM Higgs to 2 photons. The detector has 4300 silicon sensors each subdivided into 32 channels with a total sensitive area of 16.4 m2. Front-end microelectronics ASICs must measure the charge of each channel accurately with low noise and over a wide dynamic range (4 fC to 1600 fC) at the rate of 40 MHz within a harsh radiation environment. This thesis presents the design and development of the Preshower front-end electronics ASIC development, PACE. The first chapter introduces the Preshower experiment and defines the specification for PACE as derived from the physics. The second chapter examines the radiation environment, its effect on electronic devices, and design techniques / technologies that can resist to LHC radiation levels. Chapters 3 to 5 present the design and results of two PACE developments examining analog memories based on current and voltage sampling techniques. Experimental results from a Preshower electro-mechanical prototype tested in a particle beam are also given.
fre
CERN
Geneva
2001
http://documents.cern.ch/cgi-bin/setlink?base=preprint&categ=cern&id=cern-thesis-2001-023;
http://cds.cern.ch/record/524424/files/thesis-2001-023.pdf;
http://cds.cern.ch/record/524424/files/thesis-2001-023.ps.gz;
Imported from Invenio.
Aspell, P
Barney, D
Bloch, P
Jarron, Pierre
Löfstedt, B
Reynaud, S
Tabbers, P
Delta: a charge sensitive front-end amplifier with switched gain for low-noise, large dynamic range silicon detector readout
Nucl. Instrum. Methods Phys. Res., A
449-55
461
The design and results of a radiation hard switched gain charge amplifier optimised for a large dynamic range and large input capacitance are described. The peaking time is 25 ns, dynamic ranges are 0.1-50 minimum ionising particles (MIPs) (high gain) and 1-400 MIPs (low gain), signal to noise (S/N)>10 for C/sub m/<56 pF and radiation tolerance to 10 Mrads(Si) and 4*10/sup 13/ n cm/sup -2/. (5 refs).
eng
2001
Imported from Invenio.
Heijne, Erik H M
Jarron, Pierre
Anghinolfi, Francis
Aspell, P
Campbell, M
Faccio, F
Kaplon, J
Lemeilleur, F
Snoeys, W
Borgeaud, P
Delagnes, E
Dentan, M F
Lugiez, F
Rouger, M
Borel, G
Redolfi, J
Brice, J M
Dabrowski, W
RD9 final status report: a demonstrator analog signal processing circuit in a radiation hard SOI-CMOS technology
http://preprints.cern.ch/cgi-bin/setlink?base=SC&categ=Scientific_Proposal&id=SC00000790;
http://cds.cern.ch/record/336523/files/SC00000790.pdf;
http://cds.cern.ch/record/336523/files/SC00000790.tif;
Imported from Invenio.
Munday, D J
Parker, A
Anghinolfi, Francis
Aspell, P
Campbell, M
Jarron, Pierre
Heijne, Erik H M
Meddeler, G
Santiard, Jean-Claude
Verweij, H
Gössling, C
Bonino, R
Clark, A G
Couyoumtzelis, C
La Marra, D
Wu, X
Moorhead, G F
Weidberg, A R
Campbell, D
Murray, P
Seller, P
Stevens, R
Beuville, E
Rouget, M
Teiger, J
A 66 MHz, 32-channel analog memory circuit with data selection for fast silicon detectors
http://preprints.cern.ch/cgi-bin/setlink?base=preprint&categ=CM-P&id=CM-P00056588;
http://cds.cern.ch/record/240428/files/CM-P00056588.pdf;
Imported from Invenio.
Anghinolfi, Francis
Aspell, P
Campbell, M
Dorenbosch, Jheroen
Heijne, Erik H M
Jarron, Pierre
Meddeler, G
Olsen, A
Von der Lippe, H
HARP: hierarchical analog readout processor with analog pipelining in CMOS
http://documents.cern.ch/cgi-bin/setlink?base=yellowarticle&categ=90-10_v3&id=p284;
http://cds.cern.ch/record/232298/files/p284.pdf;
http://cds.cern.ch/record/232298/files/p284.tif;
Imported from Invenio.
Anghinolfi, Francis
Aspell, P
Campbell, M
Heijne, Erik H M
Jarron, Pierre
Verweij, H
Santiard, Jean-Claude
Analog sampling techniques in CMOS technology for future front ends
http://preprints.cern.ch/cgi-bin/setlink?base=preprint&categ=CM-P&id=CM-P00056573;
http://cds.cern.ch/record/228281/files/CM-P00056573.pdf;
Imported from Invenio.
Anghinolfi, Francis
Aspell, P
Campbell, M
Heijne, Erik H M
Jarron, Pierre
Meddeler, G
Study of analogue front-end electronics for supercollider experiments
http://documents.cern.ch/cgi-bin/setlink?base=yellowarticle&categ=90-10_v3&id=p84;
http://preprints.cern.ch/cgi-bin/setlink?base=preprint&categ=CM-P&id=CM-P00056674;
http://cds.cern.ch/record/218379/files/CM-P00056674.pdf;
http://cds.cern.ch/record/218379/files/p84.tif;
Imported from Invenio.
Aspell, P
Bates, S
Bloch, P
Grabit, R
Jarron, Pierre
Lemeilleur, F
Loos, R
Marchioro, A
Rosso, E
Badier, J
Bourotte, J
Busata, A
Busson, P
Charlot, C
Dobrzynski, Ludwik
Ferreira, O
Gregory, C
Karar, A
Manigot, P
Tanaka, R
Vanel, J C
Bityukov, S I
Obraztsov, V F
Ostankov, A P
Protopopov, Yu
Ryakalin, V
Spiridonov, P
Soushkov, V
Vasilchenko, V G
Clayton, E
Miller, D
Seez, Christopher J
Virdee, Tejinder S
Djilkibaev, R
Gninenko, S N
Guschin, E
Musienko, Yu V
Popov, V
Skasyrskaya, A
Semenyuk, I N
Cheremukhin, I
Egorov, A
Golutvin, I A
Kozlov, Yu Z
Moisenz, P V
Sergeev, S
Sidorov, A
Zubarev, E V
Zamiatin, N I
Bordalo, P
Ramos, S
Varela, J
Cockerill, D J A
Connolly, J
Denton, Lynn
Godinovic, N
Puljak, I
Soric, I
Chendvankar, S R
Sen-Gupta, S K
Ganguli, S N
Gurtu, A
Maity, M
Majumder, G
Mazumdar, K
Moulik, T
Energy and spatial resolution of a Shashlik calorimeter and a silicon preshower detector
Nucl. Instrum. Methods Phys. Res., A
17-28
376
http://preprints.cern.ch/cgi-bin/setlink?base=preprint&categ=cern&id=ppe-95-151;
http://cds.cern.ch/record/291080/files/ppe-95-151.pdf;
http://cds.cern.ch/record/291080/files/ppe-95-151.ps.gz;
Imported from Invenio.
Anghinolfi, Francis
Aspell, P
Campbell, M
Faccio, F
Glaser, M
Heijne, Erik H M
Jarron, Pierre
Lemeilleur, F
Meddeler, G
Rossi, G
Verweij, H
Status report RD9: a demonstrator analog signal processing circuit in a radiation hard SOI-CMOS technology
http://preprints.cern.ch/cgi-bin/setlink?base=SC&categ=Scientific_Proposal&id=SC00000074;
http://cds.cern.ch/record/290980/files/SC00000074.pdf;
http://cds.cern.ch/record/290980/files/SC00000074.tif;
Imported from Invenio.
Borer, K
Beringer, J
Anghinolfi, Francis
Aspell, P
Chilingarov, A G
Jarron, Pierre
Heijne, Erik H M
Santiard, Jean-Claude
Verweij, H
Gössling, C
Lisowski, B
Reichold, A
Bonino, R
Clark, A G
Kambara, H
La Marra, D
Léger, A
Wu, X
Richeux, J P
Taylor, G N
Fedotov, M G
Kuper, E A
Velikzhanin, Yu S
Campbell, D
Murray, P
Seller, P
Readout electronics development for the ATLAS silicon tracker
Nucl. Instrum. Methods Phys. Res., A
193-196
360
We present the status of the development of the readout electronics for the large area silicon tracker of the ATLAS experiment at the LHC, carried out by the CERN RD2 project. Our basic readout concept is to integrate a fast amplifier, analog memory, sparse data scan circuit and analog-to-digital convertor (ADC) on a single VLSI chip. This architecture will provide full analog information of charged particle hits associated unambiguously to one LHC beam crossing, which is expected to be at a frequency of 40 MHz. The expected low occupancy of the ATLAS inner silicon detectors allows us to use a low speed (5 MHz) on-chip ADC with a multiplexing scheme. The functionality of the fast amplifier and analog memory have been demonstrated with various prototype chips. Most recently we have successfully tested improved versions of the amplifier and the analog memory. A piecewise linear ADC has been fabricated and performed satisfactorily up to 5 MHz. A new chip including amplifier, analog memory, memory controller, ADC, and data buffer has been designed and submitted for fabrication and will be tested on a prototype of the ATLAS silicon tracker module with realistic electrical and mechanical constraints.
eng
1995
Imported from Invenio.
Borer, K
Munday, D J
Parker, M A
Anghinolfi, Francis
Aspell, P
Campbell, M
Jarron, Pierre
Heijne, Erik H M
Santiard, Jean-Claude
Verweij, H
Gössling, C
Reichold, A
Bonino, R
Clark, A G
Kambara, H
La Marra, D
Léger, A
Richeux, J P
Wu, X
Fares, F
Bibby, J H
Weidberg, A R
Campbell, D
Murray, P
Seller, P
Rouget, M
Teiger, J
APC3: a charge sampling, storage and readout chip for silicon detector readout
IEEE Trans. Nucl. Sci.
1091-1094
41
An analog memory prototype containing 8*128 cells has been designed in a commercial quarter-micron CMOS process. The aim of this work is to investigate the possibility of designing large dynamic range mixed-mode switched capacitor circuits for high-energy physics (HEP) applications in deep submicron CMOS technologies. Special layout techniques have been used to make the circuit radiation tolerant. The memory cells employ gate-oxide capacitors for storage, permitting a very high density. A voltage write-voltage read architecture has been chosen to minimize the sensitivity to absolute capacitor values. The measured input voltage range is 2.3 V (the power supply voltage V/sub DD/ is equal to 2.5 V), with a linearity of almost 8 bits over 2 V. The dynamic range is more than 11 bits. The pedestal variation is +or-0.5 mV peak-to-peak. The noise measured, which is dominated by the noise of the measurement setup, is around 0.8 mV rms. The characteristics of the memory have been measured before irradiation and after 100 kGy (SiO/sub 2/), and they do not degrade after irradiation. (15 refs).
eng
2001
http://documents.cern.ch/cgi-bin/setlink?base=generic&categ=public&id=cer-002278353;
http://cds.cern.ch/record/521706/files/cer-002278353.pdf;
Imported from Invenio.
Anghinolfi, Francis
Dabrowski, W
Delagnes, E
Kaplon, J
Kötz, U
Jarron, Pierre
Lugiez, F
Posch, C
Roe, S
Weilhammer, Peter
SCTA - A Rad-Hard BiCMOS Analogue Readout ASIC for the ATLAS Semiconductor Tracker
Two prototype chips for the analogue readout of silicon strip detectors in the ATLAS Semiconductor Tracker (SCT) have been designed and manufactured, in 32 channels and 128 channel versions, using the radiation hard BiCMOS DMILL process. The SCTA chip comprises three basic blocks: front-end amplifier, analogue pipeline and output multiplexer. The front-end circuit is a fast transresistance amplifier followed by an integrator, providing fast shaping with a peaking time of 25 ns, and an output buffer. The front end output values are sampled at 40 MHz rate and stored in a 112-cell deep analogue pipeline. The delay between the write pointer and trigger pointer is tunable between 2 ms and 2.5 ms. The chip has been tested successfully and subsequently irradiated up to 10 Mrad. Full functionality of all blocks of the chip has been achieved at a clock frequency of 40 MHz both before and after irradiation. Noise figures of ENC = 720 e- + 33 e-/pF before irradiation and 840 e- + 33 e-/pF after irradiation have been obtained.
eng
1996
http://preprints.cern.ch/cgi-bin/setlink?base=preprint&categ=cern&id=ECP-96-016;
http://cds.cern.ch/record/319822/files/ecp-96-016.pdf;
http://cds.cern.ch/record/319822/files/ecp-96-016.ps.gz;
Imported from Invenio.
Anghinolfi, Francis
Aspell, P
Campbell, M
Heijne, Erik H M
Jarron, Pierre
Meddeler, G
A demonstrator analog signal processing circuit in a radiation hard SOI-CMOS technology: summary
http://preprints.cern.ch/cgi-bin/setlink?base=SC&categ=Scientific_Proposal&id=SC00000315;
http://cds.cern.ch/record/302818/files/SC00000315.tif;
http://cds.cern.ch/record/302818/files/SC00000315.pdf;
Imported from Invenio.
Anghinolfi, Francis
Arnaudov, P
Bonino, R
Buttler, W T
Campbell, D
Clark, A
Evans, E
Gorbold, J R
Grillo, A
Haber, C
Jarron, Pierre
Kaplon, J
Kundu, N
La Marra, D
Luo, L
Milev, M
Milgrome, O
Nickerson, R B
Nygård, E
Ødegaard, T
Roe, S
Seller, P
Tyndel, M
Weidberg, T
Weilhammer, Peter
AROW: a 128 channel analogue pipeline with Wilkinson ADC and sparsification ASIC
It is proposed to develop a demonstrator integrated circuit for particle detector analog signal processing using the advanced 1.2 micron HSOI3-HD Silicon-on-Insulator (SOI) CMOS radiation hard technology of Thomson-TMS, which has recently become accessible for selected civilian applications. The characteristics announced for this process promise survivability after a total dose in excess of 10 Mrad (SiO2) and 10**14 to 10**15 n/cm2, which is probably satisfactory for applications in LHC detector systems. The properties of such a SOI process look promising, in particular regarding speed. In view of the special analog requirements in the particle physics environment,one should verify the analog characteristics before and after irradiation by producing a demonstrator signal processing circuit which incorporates the most vital functional blocks. This demonstrator would consist of a low noise front-end amplifier, a comparator and an analog pipeline element with associated logic, following the scheme of the Hierarchical Analog Readout Pipelined Processor HARP, which has been developed in the framework of the CERN-LAA detector R&D project.
eng
1990
http://preprints.cern.ch/cgi-bin/setlink?base=SC&categ=Scientific_Proposal&id=SC00000146;
http://cds.cern.ch/record/292599/files/SC00000146.pdf;
http://cds.cern.ch/record/292599/files/SC00000146.tif;
Imported from Invenio.
Anghinolfi, Francis
Aspell, P
Bonino, R
Borer, K
Campbell, D
Campbell, M
Clark, A G
Gössling, C
Jarron, Pierre
Heijne, Erik H M
Kambara, H
Lisowski, B
Moorhead, G F
Murray, P
Santiard, Jean-Claude
Taylor, G N
Teiger, J
Verweij, H
Weidberg, A R
Wu, X
Characteristics of a "HARP' signal processor with analog memory operated with segmented silicon detectors
IEEE Trans. Nucl. Sci.
1130-1134
41
http://preprints.cern.ch/cgi-bin/setlink?base=preprint&categ=CM-P&id=CM-P00049303;
http://cds.cern.ch/record/257688/files/257688.zip;
http://cds.cern.ch/record/257688/files/CM-P00049303.pdf;
Imported from Invenio.
Olsen, A
Von der Lippe, H
Jarron, Pierre
Anghinolfi, Francis
Heijne, Erik H M
A switched capacitor analogue storage line
http://cds.cern.ch/record/212105/files/678.pdf;
Imported from Invenio.