Garvey J. Hillier S. Mahout G. Moye T. H. Staley R. J. Watkins P.M. Watson A. Achenbach R. Hanke P. Kluge E-E. Meier K. Meshkov P. Nix O. Penno K. Schmitt K. Ay C. Bauss B. Dahlhoff A. Jakobs K. Mahboubi K. Schäfer U. Trefzger T. Eisenhandler E. Landon M. Moyse E. Thomas J. Apostoglou P. Barnett B. M. Brawn I.P. Davis A.O. Edwards J. Gee C. N. P. Gillman A. R. Perera V. J. O. Qian W. Bohm C. Hellman S. Hidvégi A. Silverstein S. 2003 The architecture of the ATLAS Level-1 Calorimeter Trigger system (L1Calo) is presented. Common approaches have been adopted for data distribution, result merging, readout, and slow control across the three different subsystems. A significant amount of common hardware is utilized, yielding substantial savings in cost, spares, and development effort. A custom, high-density backplane has been developed with data paths suitable for both the em/tt cluster processor (CP) and jet/energy-summation processor (JEP) subsystems. Common modules also provide interfaces to VME, CANbus and the LHC Timing, Trigger and Control system (TTC). A common data merger module (CMM) uses FPGAs with multiple configurations for summing electron/photon and tau/hadron cluster multiplicities, jet multiplicities, or total and missing transverse energy. The CMM performs both crate- and system-level merging. A common, FPGA-based readout driver (ROD) is used by all of the subsystems to send input, intermediate and output data to the data acquisition system (DAQ), and region-of-interest (RoI) data to the level-2 triggers. Extensive use of FPGAs throughout the system makes the trigger flexible and upgradeable, and several architectural choices have been made to reduce the number of inter-crate links and make the hardware more robust. INTNOTEATLASPRIV