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Video Lectures

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2025-05-23
15:44
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 The Landau Bootstrap: Progress, Challenges, and Outlook / Hannesdottir, Hofie (speaker) ; Mcleod, Andrew Jordan (speaker) (The University of Edinburgh (GB))
2025 - 4907. TH institutes; Bootstrapping Amplitudes from Weak to Strong Coupling External links: Talk details; Event details In : Bootstrapping Amplitudes from Weak to Strong Coupling

Detaljerad journal
2025-05-23
11:22
Not yet available
 SOFIA: Singularities of Feynman Integrals Automatized / Mizera, Sebastian (speaker)
2025 - 4169. TH institutes; Bootstrapping Amplitudes from Weak to Strong Coupling External links: Talk details; Event details In : Bootstrapping Amplitudes from Weak to Strong Coupling

Detaljerad journal
2025-05-23
11:22
Not yet available
 Automating Hierarchical Constraints for Feynman Integrals / Lippstreu, Luke (speaker)
2025 - 4107. TH institutes; Bootstrapping Amplitudes from Weak to Strong Coupling External links: Talk details; Event details In : Bootstrapping Amplitudes from Weak to Strong Coupling

Detaljerad journal
2025-05-23
11:22
Not yet available
 QFT as a set of ODEs / Penedones, João (speaker) (EPFL)
2025 - 4800. TH institutes; Bootstrapping Amplitudes from Weak to Strong Coupling External links: Talk details; Event details In : Bootstrapping Amplitudes from Weak to Strong Coupling

Detaljerad journal
2025-05-23
11:15
Not yet available
 Gauge Theory Bootstrap: predicting pion dynamics from QCD / He, Yifei (speaker)
2025 - 3771. TH institutes; Bootstrapping Amplitudes from Weak to Strong Coupling External links: Talk details; Event details In : Bootstrapping Amplitudes from Weak to Strong Coupling

Detaljerad journal
2025-05-23
10:38
Not yet available
 Architecting FPGA for low power Leadership / Shah, Hardik (speaker) (Lattice Semiconductor)
Reducing power consumption in FPGAs offers a range of benefits across various applications, including: extended battery life, simplified heat sink requirements, reduced complexity of the PCB power network, the potential for smaller package sizes, minimized heat-related measurement errors, and increased component longevity. Achieving energy-efficient FPGA design demands a comprehensive approach—from product strategy to the choice of process technology and on-chip architecture. [...]
2025 - 1555. FPGA Developers' Forum (FDF); 2nd FPGA Developers' Forum (FDF) meeting External links: Talk details; Event details In : 2nd FPGA Developers' Forum (FDF) meeting

Detaljerad journal
2025-05-23
10:38
Not yet available
 Get the right FPGA quality through efficient Requirements Coverage (aka Specification Coverage) / Tallaksen, Espen (speaker) (EmLogic)
**Requirements Tracking** is getting more and more attention, and is critical for safety (e.g. DO-254) and mission critical (e.g [...]
2025 - 2495. FPGA Developers' Forum (FDF); 2nd FPGA Developers' Forum (FDF) meeting External links: Talk details; Event details In : 2nd FPGA Developers' Forum (FDF) meeting

Detaljerad journal
2025-05-23
08:25
Not yet available
 Standardizing SoC Development in CERN's accelerator complex: A Build System for Xilinx Platforms / Degl'Innocenti, Irene (speaker) (CERN) ; Pinho, André (speaker) (CERN)
With the increasing adoption of SoC-based systems in CERN Accelerator and Technology sector (ATS), new initiatives have been put in place to ensure that systems of similar form share as many components (hardware, gateware and software) as possible. These initiatives are grouped by the ATS SoC Framework Project, now under development. [...]
2025 - 2151. FPGA Developers' Forum (FDF); 2nd FPGA Developers' Forum (FDF) meeting External links: Talk details; Event details In : 2nd FPGA Developers' Forum (FDF) meeting

Detaljerad journal
2025-05-23
08:25
Not yet available
 Low Jitter Frame Clock Recovery in Xilinx Ultrascale+ Transceivers / Bachek, Paul (speaker) (Brookhaven National Lab)
The Electron Ion Collider (EIC) Timing Data Link requires high precision clock recovery for accelerator master clock distribution. To meet the performance requirements a novel method for extracting a low jitter data frame clock from serial encoded data using Xilinx Ultrascale+ transceivers is presented. [...]
2025 - 1462. FPGA Developers' Forum (FDF); 2nd FPGA Developers' Forum (FDF) meeting External links: Talk details; Event details In : 2nd FPGA Developers' Forum (FDF) meeting

Detaljerad journal
2025-05-23
08:25
Not yet available
 Disruptive Efinix Quantum Architecture / Werner, Harald (speaker) (Efinix Inc.)
In this session we will explain the new disruptive architecture from our new low power, high speed FPGA Families. This architecture is different to the standard FPGA architecture and has a lot of benefits compare to the old architecture [...]
2025 - 1705. FPGA Developers' Forum (FDF); 2nd FPGA Developers' Forum (FDF) meeting External links: Talk details; Event details In : 2nd FPGA Developers' Forum (FDF) meeting

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