Enseignement technique: Comprehensive VHDL for FPGA Design' and 'Introduction au VHDL et utilisation du simulateur NCVHDL de CADENCE' course sessions, May-June 2006

The next session of the course 'Comprehensive VHDL for FPGA Design'given in English by Doulos Ltd (UK) will take place at CERN from May 29 through June 2nd (5 days), for a maximum of 14 participants. It will be preceded by an optional, refresher session of the two-day course 'Introduction au VHDL et utilisation du simulateur NCVHDL de CADENCE', given on 23-24 May, in French, by Serge Brobecker of IT/DES.

For more information, please visit the Technical Training CTA website, http://cta.cern.ch/cta2/f?p=300, to consult the detailed course descriptions and to apply via EDH.

Organiser: Davide Vitè / HR-PMD / 75141
Davide.Vite@cern.ch

ENSEIGNEMENT TECHNIQUE
TECHNICAL TRAINING
technical.training@cern.ch

par Davide Vitè