CERN Accelerating science

ATLAS Slides
Report number	ATL-DAQ-SLIDE-2012-529
Title	An FPGA based Topological Processor Prototype for the ATLAS Level-1 Trigger Upgrade
Author(s)	"Wenzel, V (Johannes Gutenberg Universitaet Mainz") ; "Bauss, B (Johannes Gutenberg Universitaet Mainz") ; "Buescher, V (Johannes Gutenberg Universitaet Mainz") ; "Degele, R (Johannes Gutenberg Universitaet Mainz") ; "Ji, W (Johannes Gutenberg Universitaet Mainz") ; "Moritz, S (Johannes Gutenberg Universitaet Mainz") ; "Reiss, A (Johannes Gutenberg Universitaet Mainz") ; "Schaefer, U (Johannes Gutenberg Universitaet Mainz") ; "Simioni, E (Johannes Gutenberg Universitaet Mainz") ; "Tapprogge, S (Johannes Gutenberg Universitaet Mainz")
Corporate author(s)	The ATLAS collaboration
Submitted to	Topical Workshop on Electronics for Particle Physics, Oxford, UK, 17 - 21 Sep 2012
Submitted by	eduard.simioni@cern.ch on 17 Sep 2012
Subject category	Detectors and Experimental Techniques
Accelerator/Facility, Experiment	CERN LHC ; ATLAS
Free keywords	Trigger ; topology ; topological algorithm ; topological ; FPGA ; TDAQ ; upgrade ; xilinx ; l1calo ; atlas ; algorithms ; bandwidth ; calorimeter ; concentrator ; demonstrators ; latency
Abstract	By 2014 the LHC will collide proton bunches at 14 TeV with an increased instantaneous luminosity up to 3×10^34cm−2s−1. A reduction on the trigger rate can be achieved by applying topological cuts adopting a new FPGA based module in the L1 trigger: the Topological Processor (TP). This presentation focuses on the design of the first TP prototype and on the test results on algorithm implemented in the TP demonstrator in order to measure latency and FPGA logic utilization.