002314731 001__ 2314731 002314731 003__ SzGeCERN 002314731 005__ 20180424220903.0 002314731 0247_ $$2DOI$$9IEEE$$a10.1109/PRIME.2017.7974142 002314731 0248_ $$aoai:inspirehep.net:1650740$$pcerncds:CERN$$qINSPIRE:HEP$$qForCDS 002314731 035__ $$9http://inspirehep.net/oai2d$$aoai:inspirehep.net:1650740$$d2018-04-23T13:21:57Z$$h2018-04-24T04:00:07Z$$mmarcxml 002314731 035__ $$9Inspire$$a1650740 002314731 041__ $$aeng 002314731 100__ $$aMarconi, Sara$$uU. Perugia (main)$$uINFN, Italy 002314731 245__ $$9IEEE$$aLow-power optimisation of a pixel array architecture for next generation High Energy Physics detectors 002314731 260__ $$c2017 002314731 300__ $$a4 p 002314731 520__ $$9IEEE$$aA large scale pixel readout chip is being designed by the RD53 Collaboration, in order to prove the suitability of 65 nm technology for the extreme operating conditions foreseen for the High Luminosity upgrades of the ATLAS and CMS experiments at CERN. The use of advanced digital design and simulation tools is essential to guide architectural and implementation choices for the design and optimisation of pixel chips which will be powered from a serial powering scheme. In this work, low power design techniques are reviewed and critically selected based on the requirements of the target application. Chosen techniques are adopted and results of the low power optimisation are presented for a basic unit of the system. 002314731 65017 $$2SzGeCERN$$aDetectors and Experimental Techniques 002314731 6531_ $$9author$$aClocks 002314731 6531_ $$9author$$aOptimization 002314731 6531_ $$9author$$aLatches 002314731 6531_ $$9author$$aIntegrated circuits 002314731 6531_ $$9author$$aPower demand 002314731 6531_ $$9author$$aSwitching circuits 002314731 6531_ $$9author$$aDegradation 002314731 6531_ $$9author$$aimage sensors 002314731 6531_ $$9author$$alow-power electronics 002314731 6531_ $$9author$$areadout electronics 002314731 6531_ $$9author$$alow-power optimisation 002314731 6531_ $$9author$$apixel array architecture 002314731 6531_ $$9author$$anext generation high-energy physics detectors 002314731 6531_ $$9author$$alarge-scale pixel readout chip 002314731 6531_ $$9author$$aRD53 collaboration 002314731 6531_ $$9author$$ahigh-luminosity upgrades 002314731 6531_ $$9author$$aATLAS 002314731 6531_ $$9author$$aCMS experiment 002314731 6531_ $$9author$$aCERN 002314731 6531_ $$9author$$aadvanced digital design tool 002314731 6531_ $$9author$$asimulation tool 002314731 6531_ $$9author$$aarchitectural choice 002314731 6531_ $$9author$$aimplementation choice 002314731 6531_ $$9author$$apixel chip design 002314731 6531_ $$9author$$apixel chip optimisation 002314731 6531_ $$9author$$aserial powering scheme 002314731 6531_ $$9author$$alow-power design technique 002314731 6531_ $$9author$$asize 65 nm 002314731 690C_ $$aCERN 002314731 693__ $$aNot applicable$$eRD53 002314731 700__ $$aHemperek, Tomasz$$uBonn U. 002314731 700__ $$aPlacidi, Pisana$$uU. Perugia (main)$$uINFN, Italy 002314731 700__ $$aScorzoni, Andrea$$uU. Perugia (main)$$uINFN, Italy 002314731 700__ $$aConti, Elia$$uCERN 002314731 700__ $$aChristiansen, Jorgen$$uCERN 002314731 773__ $$c201-204$$wC17-06-12.6$$y2017 002314731 960__ $$a13 002314731 962__ $$b2313047$$k201-204$$ntaormina20170612 002314731 980__ $$aARTICLE 002314731 980__ $$aConferencePaper 002314731 999C6 $$a0-0-1-1-0-0-0$$t2018-03-29 10:06:49$$vInvenio/1.1.2.1260-aa76f refextract/1.5.44 002314731 999C5 $$01506504$$hN. Demaria et al.$$o1$$sJINST,11,C12058$$tRecent progress of RD53 Collaboration towards next generation Pixel Read-Out Chip for HL-LHC$$y2016 002314731 999C5 $$hY. Hung-Yi$$mProc. Int. Symp. VLSI Design Autom. and Test, pp. 1-3$$o2$$tHighly automated and efficient simulation environment with UVM$$y2014 002314731 999C5 $$hJ. Rabaey$$mLow Power Design Essentials, New York, USA:$$o3$$pSpringer$$y2009 002314731 999C5 $$9CURATOR$$hP. Bipul, C., A. Agarwal, K. Roy$$mIntegration, the VLSI Journal, vol. 39, no. 2, pp. 64-89$$o4$$tLow-power design techniques for scaled technologies$$y2006 002314731 999C5 $$01090785$$hL. Gonella, M. Barbero, F. Hgging, H. Krger, N. Wermes$$o5$$sJINST,7,C01034$$tThe shunt-LDO regulator to power the upgraded ATLAS pixel detector$$y2012 002314731 999C5 $$hS. Marconi, S. Orfanelli, M. Karagounis, T. Hemperek, J. Christiansen, P. Placidi$$o6$$sJINST,12,1-9$$tAn Advanced Power Analysis Methodology Targeted to the Optimization of a Digital Pixel Readout Chip Design and its Critical Serial Powering System$$y2016 002314731 999C5 $$0825736$$hD. Arutinov et al.$$o7$$sIEEE Trans.Nucl.Sci.,56,388-393$$tDigital architecture and interface of the new ATLAS pixel front-end IC for upgraded LHC luminosity$$y2009 002314731 999C5 $$9CURATOR$$hY. H. Chen, Y. L. Tang, Y. Y. Liu, A. C. H. Wu, T. Hwang$$mIEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 25, no. 3, pp. 820-832$$o8$$tA Novel Cache-Utilization-Based Dynamic Voltage-Frequency Scaling Mechanism for Reliability Enhancements$$y2017 002314731 999C5 $$hL. M. Jara Casas et al.$$o9$$sJINST,12,1-9$$tCharacterization of radiation effects in 65 nm digital circuits with the DRAD digital radiation test chip$$y2016 002314731 999C5 $$hJ. Shinde, S. S. Salankar$$mAnnual India Conference, pp. 1-4$$o10$$pIEEE$$tClock gating - A power optimizing technique for VLSI circuits$$y2011 002314731 999C5 $$hW. Zhang, T. H. Chen, M. Y. Ting, X. Li$$mDesign Automation Conference, pp. 897-902$$o11$$tToward efficient large-scale performance modeling of integrated circuits via multi-mode/multi-corner sparse regression$$y2010 002314731 999C5 $$hE. Conti, S. Marconi, J. Christiansen, P. Placidi, T. Hemperek$$o12$$sJINST,11,1-9$$tSimulation of Digital Pixel Readout Chip Architectures with the RD53 SystemVerilog-UVM Verification Environment Using Monte Carlo Physics Data$$y2015