CERN Accelerating science

ATLAS Note
Report number	ATL-DAQ-PROC-2012-056
Title	An FPGA based topological processor prototype for the ATLAS Level-1 trigger upgrade
Author(s)	Bauss, B (Mainz U., Inst. Phys.) ; Buescher, V (Mainz U., Inst. Phys.) ; Degele, R (Mainz U., Inst. Phys.) ; Ji, W (Mainz U., Inst. Phys.) ; Moritz, S (Mainz U., Inst. Phys.) ; Reiss, A (Mainz U., Inst. Phys.) ; Schaefer, U (Mainz U., Inst. Phys.) ; Simioni, E (Mainz U., Inst. Phys.) ; Tapprogge, S (Mainz U., Inst. Phys.) ; Wenzel, V (Mainz U., Inst. Phys.)
Corporate Author(s)	The ATLAS collaboration
Publication	2012
Imprint	30 Oct 2012
Number of pages	9
In:	Topical Workshop on Electronics for Particle Physics, Oxford, UK, 17 - 21 Sep 2012
Subject category	Detectors and Experimental Techniques
Accelerator/Facility, Experiment	CERN LHC ; ATLAS
Free keywords	Level-1 Trigger ; Level-1 Calorimeter Trigger ; Topology ; topological algorithm ; FPGA ; ATLAS ; latency measurement ; Trigger Upgrade
Abstract	By 2014 the LHC will collide proton bunches at 14TeV with an increased instantaneous luminosity up to 3·10³⁴cm⁻²s⁻¹. The resulting higher event rate will challenge the existing ATLAS trigger system. A reduction on the trigger rate can be achieved by selecting interesting channels based on their expected decay topology and thus reducing background. This will be achieved by introducing of a new FPGA based module in the Level-1 trigger: the Topological Processor L1Topo. With L1Topo it will be possible for the first time to concentrate detailed information from the entire calorimeters and the muon detector into a single module. L1Topo will receive a total aggregate bandwidth of 1Tb/s. The data is processed within less than 100ns, requiring high density optical I/O and high bandwidth, which is achieved by adopting state-of-the-art FPGAs with embedded multi-Gb/s transceivers and multi-Gb/s opto converters. This paper focuses on the design of the first L1Topo prototype. The L1Topo design adopts technologies that have been implemented into a previous ATCA form factor demonstrator module. The latest results on the implementation of a topological algorithm in the demonstrator module and FPGA logic utilization of the algorithm are presented. Beyond results of a measurement of the latency, induced by the demonstrator module's FPGA's integrated Multi-Gb/s transceivers, are reported.
Copyright/License	Preprint: (License: CC-BY-4.0)