1 Recent progress of RD53 Collaboration towards next generation Pixel Read-Out Chip for HL-LHC2016
2 Proc. Int. Symp. VLSI Design Autom. and Test, pp. 1-3 Highly automated and efficient simulation environment with UVM2014
3 Low Power Design Essentials, New York, USA: 4 Integration, the VLSI Journal, vol. 39, no. 2, pp. 64-89 Low-power design techniques for scaled technologies2006
5 The shunt-LDO regulator to power the upgraded ATLAS pixel detector2012
6 An Advanced Power Analysis Methodology Targeted to the Optimization of a Digital Pixel Readout Chip Design and its Critical Serial Powering System2016
7 Digital architecture and interface of the new ATLAS pixel front-end IC for upgraded LHC luminosity2009
8 IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 25, no. 3, pp. 820-832 A Novel Cache-Utilization-Based Dynamic Voltage-Frequency Scaling Mechanism for Reliability Enhancements2017
9 Characterization of radiation effects in 65 nm digital circuits with the DRAD digital radiation test chip2016
10 Annual India Conference, pp. 1-4 Clock gating - A power optimizing technique for VLSI circuits2011IEEE
11 Design Automation Conference, pp. 897-902 Toward efficient large-scale performance modeling of integrated circuits via multi-mode/multi-corner sparse regression2010
12 Simulation of Digital Pixel Readout Chip Architectures with the RD53 SystemVerilog-UVM Verification Environment Using Monte Carlo Physics Data2015